upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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92 lines
2.9 KiB
92 lines
2.9 KiB
13 years ago
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/*
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* (C) Copyright 2011
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* Linaro
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* Linus Walleij <linus.walleij@linaro.org>
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* Register definitions for the System Controller (SC) and
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* the similar "CP Controller" found in the ARM Integrator/AP and
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* Integrator/CP reference designs
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ARM_SC_H
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#define __ARM_SC_H
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#define SC_BASE 0x11000000
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/*
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* The system controller registers
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*/
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#define SC_ID_OFFSET 0x00
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#define SC_OSC_OFFSET 0x04
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/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
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#define SC_OSC_DIVXY (1 << 8)
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#define SC_CTRLS_OFFSET 0x08
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#define SC_CTRLC_OFFSET 0x0C
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/* Set bits by writing CTRLS, clear bits by writing CTRLC */
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#define SC_CTRL_SOFTRESET (1 << 0)
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#define SC_CTRL_FLASHVPP (1 << 1)
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#define SC_CTRL_FLASHWP (1 << 2)
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#define SC_CTRL_UART1DTR (1 << 4)
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#define SC_CTRL_UART1RTS (1 << 5)
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#define SC_CTRL_UART0DTR (1 << 6)
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#define SC_CTRL_UART0RTS (1 << 7)
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#define SC_DEC_OFFSET 0x10
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#define SC_ARB_OFFSET 0x14
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#define SC_PCI_OFFSET 0x18
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#define SC_PCI_PCIEN (1 << 0)
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#define SC_PCI_PCIBINT_CLR (1 << 1)
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#define SC_LOCK_OFFSET 0x1C
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#define SC_LBFADDR_OFFSET 0x20
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#define SC_LBFCODE_OFFSET 0x24
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#define SC_ID (SC_BASE + SC_ID_OFFSET)
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#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
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#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
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#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
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#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
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#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
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#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
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#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
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#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
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#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
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/*
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* The Integrator/CP as a smaller set of registers, at a different
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* offset - probably not to disturb old software.
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*/
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#define CP_BASE 0xCB000000
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#define CP_IDFIELD_OFFSET 0x00
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#define CP_FLASHPROG_OFFSET 0x04
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#define CP_FLASHPROG_FLVPPEN (1 << 0)
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#define CP_FLASHPROG_FLWREN (1 << 1)
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#define CP_FLASHPROG_FLASHSIZE (1 << 2)
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#define CP_FLASHPROG_EXTRABANK (1 << 3)
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#define CP_INTREG_OFFSET 0x08
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#define CP_DECODE_OFFSET 0x0C
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#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
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#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
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#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
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#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
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#endif
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