upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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293 lines
6.6 KiB
293 lines
6.6 KiB
13 years ago
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/*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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/* Every register is 32bit aligned, but only 8bits in size */
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#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
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struct sh_i2c {
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ureg(icdr);
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ureg(iccr);
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ureg(icsr);
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ureg(icic);
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ureg(iccl);
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ureg(icch);
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};
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#undef ureg
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static struct sh_i2c *base;
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/* ICCR */
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#define SH_I2C_ICCR_ICE (1 << 7)
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#define SH_I2C_ICCR_RACK (1 << 6)
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#define SH_I2C_ICCR_RTS (1 << 4)
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#define SH_I2C_ICCR_BUSY (1 << 2)
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#define SH_I2C_ICCR_SCP (1 << 0)
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/* ICSR / ICIC */
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#define SH_IC_BUSY (1 << 3)
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#define SH_IC_TACK (1 << 2)
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#define SH_IC_WAIT (1 << 1)
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#define SH_IC_DTE (1 << 0)
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static u8 iccl, icch;
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#define IRQ_WAIT 1000
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static void irq_wait(struct sh_i2c *base)
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{
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int i;
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u8 status;
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for (i = 0 ; i < IRQ_WAIT ; i++) {
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status = readb(&base->icsr);
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if (SH_IC_WAIT & status)
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break;
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udelay(10);
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}
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writeb(status & ~SH_IC_WAIT, &base->icsr);
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}
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static void irq_dte(struct sh_i2c *base)
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{
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int i;
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for (i = 0 ; i < IRQ_WAIT ; i++) {
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if (SH_IC_DTE & readb(&base->icsr))
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break;
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udelay(10);
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}
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}
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static void irq_busy(struct sh_i2c *base)
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{
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int i;
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for (i = 0 ; i < IRQ_WAIT ; i++) {
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if (!(SH_IC_BUSY & readb(&base->icsr)))
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break;
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udelay(10);
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}
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}
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static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
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{
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writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
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writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr);
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writeb(iccl, &base->iccl);
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writeb(icch, &base->icch);
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writeb(0, &base->icic);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
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irq_dte(base);
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writeb(id << 1, &base->icdr);
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irq_dte(base);
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writeb(reg, &base->icdr);
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if (stop)
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
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irq_dte(base);
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}
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static void i2c_finish(struct sh_i2c *base)
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{
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writeb(0, &base->icsr);
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writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
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}
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static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
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{
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i2c_set_addr(base, id, reg, 0);
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udelay(10);
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writeb(val, &base->icdr);
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irq_dte(base);
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writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
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irq_dte(base);
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irq_busy(base);
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i2c_finish(base);
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}
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static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
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{
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u8 ret;
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i2c_set_addr(base, id, reg, 1);
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udelay(100);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
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irq_dte(base);
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writeb(id << 1 | 0x01, &base->icdr);
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irq_dte(base);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
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irq_dte(base);
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ret = readb(&base->icdr);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
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readb(&base->icdr); /* Dummy read */
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irq_busy(base);
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i2c_finish(base);
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return ret;
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}
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#ifdef CONFIG_I2C_MULTI_BUS
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static unsigned int current_bus;
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/**
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* i2c_set_bus_num - change active I2C bus
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* @bus: bus index, zero based
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* @returns: 0 on success, non-0 on failure
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*/
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int i2c_set_bus_num(unsigned int bus)
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{
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if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
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printf("Bad bus: %d\n", bus);
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return -1;
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}
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switch (bus) {
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case 0:
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base = (void *)CONFIG_SH_I2C_BASE0;
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break;
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case 1:
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base = (void *)CONFIG_SH_I2C_BASE1;
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break;
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default:
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return -1;
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}
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current_bus = bus;
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return 0;
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}
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/**
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* i2c_get_bus_num - returns index of active I2C bus
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*/
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unsigned int i2c_get_bus_num(void)
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{
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return current_bus;
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}
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#endif
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#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
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((clk / rate) * (t_low / t_low + t_high))
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#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
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((clk / rate) * (t_high / t_low + t_high))
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void i2c_init(int speed, int slaveaddr)
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{
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int num, denom, tmp;
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#ifdef CONFIG_I2C_MULTI_BUS
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current_bus = 0;
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#endif
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base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
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/*
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* Calculate the value for iccl. From the data sheet:
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* iccl = (p-clock / transfer-rate) * (L / (L + H))
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* where L and H are the SCL low and high ratio.
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*/
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num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
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denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
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tmp = num * 10 / denom;
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if (tmp % 10 >= 5)
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iccl = (u8)((num/denom) + 1);
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else
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iccl = (u8)(num/denom);
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/* Calculate the value for icch. From the data sheet:
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icch = (p clock / transfer rate) * (H / (L + H)) */
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num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
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tmp = num * 10 / denom;
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if (tmp % 10 >= 5)
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icch = (u8)((num/denom) + 1);
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else
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icch = (u8)(num/denom);
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}
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/*
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* i2c_read: - Read multiple bytes from an i2c device
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*
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* The higher level routines take into account that this function is only
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* called with len < page length of the device (see configuration file)
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*
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* @chip: address of the chip which is to be read
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* @addr: i2c data address within the chip
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* @alen: length of the i2c data address (1..2 bytes)
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* @buffer: where to write the data
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* @len: how much byte do we want to read
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* @return: 0 in case of success
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*/
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int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
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{
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int i = 0;
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for (i = 0 ; i < len ; i++)
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buffer[i] = i2c_raw_read(base, chip, addr + i);
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return 0;
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}
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/*
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* i2c_write: - Write multiple bytes to an i2c device
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*
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* The higher level routines take into account that this function is only
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* called with len < page length of the device (see configuration file)
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*
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* @chip: address of the chip which is to be written
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* @addr: i2c data address within the chip
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* @alen: length of the i2c data address (1..2 bytes)
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* @buffer: where to find the data to be written
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* @len: how much byte do we want to read
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* @return: 0 in case of success
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*/
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int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
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{
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int i = 0;
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for (i = 0; i < len ; i++)
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i2c_raw_write(base, chip, addr + i, buffer[i]);
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return 0;
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}
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/*
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* i2c_probe: - Test if a chip answers for a given i2c address
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*
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* @chip: address of the chip which is searched for
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* @return: 0 if a chip was found, -1 otherwhise
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*/
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int i2c_probe(u8 chip)
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{
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return 0;
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}
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