upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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39 lines
1.4 KiB
39 lines
1.4 KiB
17 years ago
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/*
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* PPI Masks
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*/
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#ifndef __BFIN_PERIPHERAL_PPI__
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#define __BFIN_PERIPHERAL_PPI__
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/* PPI_CONTROL Masks */
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#define PORT_EN 0x0001 /* PPI Port Enable */
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#define PORT_DIR 0x0002 /* PPI Port Direction */
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#define XFR_TYPE 0x000C /* PPI Transfer Type */
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#define PORT_CFG 0x0030 /* PPI Port Configuration */
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#define FLD_SEL 0x0040 /* PPI Active Field Select */
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#define PACK_EN 0x0080 /* PPI Packing Mode */
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#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
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#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
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#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
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#define DLENGTH 0x3800 /* PPI Data Length */
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#define DLEN_8 0x0000 /* Data Length = 8 Bits */
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#define DLEN_10 0x0800 /* Data Length = 10 Bits */
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#define DLEN_11 0x1000 /* Data Length = 11 Bits */
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#define DLEN_12 0x1800 /* Data Length = 12 Bits */
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#define DLEN_13 0x2000 /* Data Length = 13 Bits */
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#define DLEN_14 0x2800 /* Data Length = 14 Bits */
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#define DLEN_15 0x3000 /* Data Length = 15 Bits */
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#define DLEN_16 0x3800 /* Data Length = 16 Bits */
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#define POLC 0x4000 /* PPI Clock Polarity */
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#define POLS 0x8000 /* PPI Frame Sync Polarity */
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/* PPI_STATUS Masks */
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#define FLD 0x0400 /* Field Indicator */
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#define FT_ERR 0x0800 /* Frame Track Error */
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#define OVR 0x1000 /* FIFO Overflow Error */
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#define UNDR 0x2000 /* FIFO Underrun Error */
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#define ERR_DET 0x4000 /* Error Detected Indicator */
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#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
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#endif
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