upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/board/micronas/vct/bcu.h

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3.8 KiB

/*
* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
*
* Copyright (C) 2006 Micronas GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BCU_H
#define _BCU_H
enum bcu_tags {
BCU_VBV1 = 0,
BCU_VBV2 = 1,
BCU_BSS1 = 2,
BCU_BSS2 = 3,
BCU_TSD_TXT = 4,
BCU_TSD_SUBTITLES = 5,
BCU_TSD_PES_0 = 6,
BCU_TSD_PES_1 = 7,
BCU_TSD_PES_2 = 8,
BCU_TSD_PES_3 = 9,
BCU_TSIO_RECORD_0 = 10,
BCU_TSIO_RECORD_1 = 11,
BCU_TSIO_PLAYBACK_0 = 12,
BCU_TSIO_PLAYBACK_1 = 13,
BCU_SECURE_BUFFER = 14,
BCU_PCM1 = 15,
BCU_PCM2 = 16,
BCU_BSS_COPY = 17,
BCU_BSS_EXT1 = 18,
BCU_BSS_EXT2 = 19,
BCU_PCM_JINGLE = 20,
BCU_EBI_CPU_BUFFER = 21,
BCU_PCM_DELAY = 22,
BCU_FH_BUFFER_0 = 23,
BCU_FH_BUFFER_1 = 24,
BCU_TSD_SECTION_0 = 25,
BCU_TSD_SECTION_1 = 26,
BCU_TSD_SECTION_2 = 27,
BCU_TSD_SECTION_3 = 28,
BCU_TSD_SECTION_4 = 29,
BCU_TSD_SECTION_5 = 30,
BCU_TSD_SECTION_6 = 31,
BCU_TSD_SECTION_7 = 32,
BCU_TSD_SECTION_8 = 33,
BCU_TSD_SECTION_9 = 34,
BCU_TSD_SECTION_10 = 35,
BCU_TSD_SECTION_11 = 36,
BCU_TSD_SECTION_12 = 37,
BCU_TSD_SECTION_13 = 38,
BCU_TSD_SECTION_14 = 39,
BCU_TSD_SECTION_15 = 40,
BCU_TSD_SECTION_16 = 41,
BCU_TSD_SECTION_17 = 42,
BCU_TSD_SECTION_18 = 43,
BCU_TSD_SECTION_19 = 44,
BCU_TSD_SECTION_20 = 45,
BCU_TSD_SECTION_21 = 46,
BCU_TSD_SECTION_22 = 47,
BCU_TSD_SECTION_23 = 48,
BCU_TSD_SECTION_24 = 49,
BCU_TSD_SECTION_25 = 50,
BCU_TSD_SECTION_26 = 51,
BCU_TSD_SECTION_27 = 52,
BCU_TSD_SECTION_28 = 53,
BCU_TSD_SECTION_29 = 54,
BCU_TSD_SECTION_30 = 55,
BCU_TSD_SECTION_31 = 56,
BCU_TSD_SECTION_32 = 57,
BCU_TSD_SECTION_33 = 58,
BCU_TSD_SECTION_34 = 59,
BCU_TSD_SECTION_35 = 60,
BCU_TSD_SECTION_36 = 61,
BCU_TSD_SECTION_37 = 62,
BCU_TSD_SECTION_38 = 63,
BCU_TSD_SECTION_39 = 64,
BCU_TSD_SECTION_40 = 65,
BCU_TSD_SECTION_41 = 66,
BCU_TSD_SECTION_42 = 67,
BCU_TSD_SECTION_43 = 68,
BCU_TSD_SECTION_44 = 69,
BCU_TSD_SECTION_45 = 70,
BCU_TSD_SECTION_46 = 71,
BCU_TSD_SECTION_47 = 72,
BCU_TSD_SECTION_48 = 73,
BCU_TSD_SECTION_49 = 74,
BCU_TSD_SECTION_50 = 75,
BCU_TSD_SECTION_51 = 76,
BCU_TSD_SECTION_52 = 77,
BCU_TSD_SECTION_53 = 78,
BCU_TSIO_RECORD_2 = 79,
BCU_TSIO_RECORD_3 = 80,
BCU_TSIO_RECORD_4 = 81,
BCU_TSIO_RECORD_5 = 82,
BCU_TSIO_RECORD_6 = 83,
BCU_TSIO_RECORD_7 = 84,
BCU_TSIO_RECORD_8 = 85,
BCU_TSIO_RECORD_9 = 86,
BCU_PCM_DELAY_LINEAR = 87,
BCU_VD_MASTER_USER_DATA = 88,
BCU_VD_SLAVE_USER_DATA = 89,
BCU_VD_MASTER_REF0 = 90,
BCU_VD_MASTER_REF1 = 91,
BCU_VD_SLAVE_REF0 = 92,
BCU_VD_SLAVE_REF1 = 93,
BCU_VD_MASTER_DISP0_Y = 94,
BCU_VD_MASTER_DISP1_Y = 95,
BCU_VD_MASTER_DISP2_Y = 96,
BCU_VD_MASTER_DISP0_C = 97,
BCU_VD_MASTER_DISP1_C = 98,
BCU_VD_MASTER_DISP2_C = 99,
BCU_VD_SLAVE_DISP0_Y = 100,
BCU_VD_SLAVE_DISP1_Y = 101,
BCU_VD_SLAVE_DISP2_Y = 102,
BCU_VD_SLAVE_DISP0_C = 103,
BCU_VD_SLAVE_DISP1_C = 104,
BCU_VD_SLAVE_DISP2_C = 105,
BCU_CLUT_BUFFER_0 = 106,
BCU_CLUT_BUFFER_1 = 107,
BCU_OSD_FRAME_BUFFER_0 = 108,
BCU_OSD_FRAME_BUFFER_1 = 109,
BCU_GRAPHIC_FRAME_BUFFER0 = 110,
BCU_GRAPHIC_FRAME_BUFFER1 = 111,
BCU_DVP_VBI_REINSERTION = 112,
BCU_DVP_OSD_FRAME_BUFFER0 = 113,
BCU_DVP_OSD_FRAME_BUFFER1 = 114,
BCU_GAI_BUFFER = 115,
BCU_GA_SRC_BUFFER_0 = 116,
BCU_GA_SRC_BUFFER_1 = 117,
BCU_USB_BUFFER_0 = 118,
BCU_USB_BUFFER_1 = 119,
BCU_FE_3DCOMB_0 = 120,
BCU_FE_3DCOMB_1 = 121,
BCU_FE_3DCOMB_2 = 122,
BCU_FE_3DCOMB_3 = 123,
BCU_TNR_BUFFER_0 = 124,
BCU_TNR_BUFFER_1 = 125,
BCU_TNR_BUFFER_2 = 126,
BCU_MVAL_BUFFER = 127,
BCU_RC_BUFFER_0 = 128,
BCU_RC_BUFFER_1 = 129,
BCU_RC_BUFFER_2 = 130,
BCU_RC_BUFFER_3 = 131,
BCU_PIP_BUFFER_0 = 132,
BCU_PIP_BUFFER_1 = 133,
BCU_PIP_BUFFER_2 = 134,
BCU_PIP_BUFFER_3 = 135,
BCU_EWARP_BUFFER = 136,
BCU_OSD_BUFFER_0 = 137,
BCU_OSD_BUFFER_1 = 138,
BCU_GLOBAL_BUFFER_0 = 139,
BCU_GLOBAL_BUFFER_1 = 140,
BCU_MAX = 141
};
#endif /* _BCU_H */