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/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARCH_ARM_MPCORE_H
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#define ARCH_ARM_MPCORE_H
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/* Snoop Control Unit */
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#define SCU_OFFSET 0x00
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/* SCU Control Register */
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#define SCU_CTRL 0x00
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#define SCU_ENABLE (1 << 0)
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#define SCU_STANDBY_ENABLE (1 << 5)
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/* SCU Configuration Register */
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#define SCU_CONF 0x04
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/* SCU CPU Power Status Register */
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#define SCU_PWR_STATUS 0x08
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/* SCU Invalidate All Registers in Secure State */
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#define SCU_INV_ALL 0x0C
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/* SCU Filtering Start Address Register */
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#define SCU_FILTER_START 0x40
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/* SCU Filtering End Address Register */
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#define SCU_FILTER_END 0x44
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/* SCU Access Control Register */
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#define SCU_SAC 0x50
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/* SCU Non-secure Access Control Register */
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#define SCU_SNSAC 0x54
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/* Global Timer */
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#define GLOBAL_TIMER_OFFSET 0x200
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/* Global Timer Counter Registers */
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#define GTIMER_CNT_L 0x00
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#define GTIMER_CNT_H 0x04
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/* Global Timer Control Register */
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#define GTIMER_CTRL 0x08
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/* Global Timer Interrupt Status Register */
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#define GTIMER_STAT 0x0C
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/* Comparator Value Registers */
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#define GTIMER_CMP_L 0x10
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#define GTIMER_CMP_H 0x14
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/* Auto-increment Register */
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#define GTIMER_INC 0x18
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#endif /* ARCH_ARM_MPCORE_H */
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