upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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266 lines
6.8 KiB
266 lines
6.8 KiB
15 years ago
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/*
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* Copyright (C) 2009 Samsung Electrnoics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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.globl mem_ctrl_asm_init
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mem_ctrl_asm_init:
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cmp r7, r8
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ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000
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ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000
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ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000
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/* DLL parameter setting */
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ldr r1, =0x50101000
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str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
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strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
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ldr r1, =0x000000f4
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str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET
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strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET
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ldreq r1, =0x0
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streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET
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/* DLL on */
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ldr r1, =0x50101002
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str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
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strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
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/* DLL start */
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ldr r1, =0x50101003
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str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
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strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
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mov r2, #0x4000
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wait: subs r2, r2, #0x1
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cmp r2, #0x0
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bne wait
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cmp r7, r8
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/* Force value locking for DLL off */
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str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
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strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
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/* DLL off */
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ldr r1, =0x50101009
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str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
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strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
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/* auto refresh off */
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ldr r1, =0xff001010 | (1 << 7)
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ldr r2, =0xff001010 | (1 << 7)
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str r1, [r0, #0x000] @ CONCONTROL_OFFSET
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strne r2, [r6, #0x000] @ CONCONTROL_OFFSET
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/*
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* Burst Length 4, 2 chips, 32-bit, LPDDR
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* OFF: dynamic self refresh, force precharge, dynamic power down off
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*/
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ldr r1, =0x00212100
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ldr r2, =0x00212100
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str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
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strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET
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/*
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* Note:
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* If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
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* So finally Bank1 OneDRAM should address start at at 0x3000'0000
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*/
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/*
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* DMC0: CS0 : S5PC100/S5PC110
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* 0x30 -> 0x30000000
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* 0xf8 -> 0x37FFFFFF
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* [15:12] 0: Linear
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* [11:8 ] 2: 9 bits
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* [ 7:4 ] 2: 14 bits
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* [ 3:0 ] 2: 4 banks
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*/
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ldr r3, =0x30f80222
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ldr r4, =0x40f00222
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swap_memory:
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str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET
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str r4, [r0, #0x00C] @ dummy write
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/*
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* DMC1: CS0 : S5PC110
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* 0x40 -> 0x40000000
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* 0xf8 -> 0x47FFFFFF (1Gib)
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* 0x40 -> 0x40000000
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* 0xf0 -> 0x4FFFFFFF (2Gib)
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* [15:12] 0: Linear
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* [11:8 ] 2: 9 bits - Col (1Gib)
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* [11:8 ] 3: 10 bits - Col (2Gib)
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* [ 7:4 ] 2: 14 bits - Row
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* [ 3:0 ] 2: 4 banks
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*/
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/* Default : 2GiB */
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ldr r4, =0x40f01322 @ 2Gib: MCP B
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ldr r5, =0x50f81312 @ dummy: MCP D
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cmp r9, #1
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ldreq r4, =0x40f81222 @ 1Gib: MCP A
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cmp r9, #3
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ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D
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cmp r9, #4
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ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E
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cmp r7, r8
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strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET
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strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET
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/*
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* DMC0: CS1: S5PC100
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* 0x38 -> 0x38000000
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* 0xf8 -> 0x3fFFFFFF
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* [15:12] 0: Linear
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* [11:8 ] 2: 9 bits
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* [ 7:4 ] 2: 14 bits
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* [ 3:0 ] 2: 4 banks
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*/
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eoreq r3, r3, #0x08000000
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streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET
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ldr r1, =0x20000000
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str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
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strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
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strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET
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/*
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* S5PC100:
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* DMC: CS0: 166MHz
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* CS1: 166MHz
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* S5PC110:
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* DMC0: CS0: 166MHz
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* DMC1: CS0: 200MHz
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*
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* 7.8us * 200MHz %LE %LONG1560(0x618)
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* 7.8us * 166MHz %LE %LONG1294(0x50E)
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* 7.8us * 133MHz %LE %LONG1038(0x40E),
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* 7.8us * 100MHz %LE %LONG780(0x30C),
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*/
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ldr r1, =0x0000050E
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str r1, [r0, #0x030] @ TIMINGAREF_OFFSET
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ldrne r1, =0x00000618
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strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET
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ldr r1, =0x14233287
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str r1, [r0, #0x034] @ TIMINGROW_OFFSET
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ldrne r1, =0x182332c8
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strne r1, [r6, #0x034] @ TIMINGROW_OFFSET
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ldr r1, =0x12130005
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str r1, [r0, #0x038] @ TIMINGDATA_OFFSET
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ldrne r1, =0x13130005
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strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET
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ldr r1, =0x0E140222
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str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET
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ldrne r1, =0x0E180222
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strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET
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/* chip0 Deselect */
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ldr r1, =0x07000000
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip0 PALL */
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ldr r1, =0x01000000
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip0 REFA */
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ldr r1, =0x05000000
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip0 REFA */
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip0 MRS */
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ldr r1, =0x00000032
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip0 EMRS */
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ldr r1, =0x00020020
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip1 Deselect */
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ldr r1, =0x07100000
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip1 PALL */
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ldr r1, =0x01100000
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip1 REFA */
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ldr r1, =0x05100000
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip1 REFA */
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip1 MRS */
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ldr r1, =0x00100032
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* chip1 EMRS */
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ldr r1, =0x00120020
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str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
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strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
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/* auto refresh on */
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ldr r1, =0xFF002030 | (1 << 7)
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str r1, [r0, #0x000] @ CONCONTROL_OFFSET
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strne r1, [r6, #0x000] @ CONCONTROL_OFFSET
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/* PwrdnConfig */
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ldr r1, =0x00100002
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str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET
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strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET
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ldr r1, =0x00212113
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str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
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strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET
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/* Skip when S5PC110 */
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bne 1f
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/* Check OneDRAM access area at s5pc100 */
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ldreq r3, =0x38f80222
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ldreq r1, =0x37ffff00
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str r3, [r1]
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ldr r2, [r1]
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cmp r2, r3
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beq swap_memory
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1:
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mov pc, lr
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.ltorg
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