upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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290 lines
9.5 KiB
290 lines
9.5 KiB
22 years ago
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#ifndef _ASM_HYMOD_H_
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#define _ASM_HYMOD_H_
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#include <linux/config.h>
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#ifdef CONFIG_8260
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#include <asm/iopin_8260.h>
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#endif
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/*
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* hymod configuration data - passed by boot code via the board information
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* structure (only U-Boot has support for this at the moment)
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*
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* there are three types of data passed up from the boot monitor. the first
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* (type hymod_eeprom_t) is the eeprom data that was read off both the main
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* (or mother) board and the mezzanine board (if any). this data defines how
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* many Xilinx fpgas are on each board, and their types (among other things).
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* the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
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* in the physical address space the various Xilinx fpga access regions have
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* been mapped by the boot rom. the third type of data (type xlx_iopins_t,
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* one per Xilinx fpga) defines which io port pins are connected to the various
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* signals required to program a Xilinx fpga.
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*
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* A ram/flash "bank" refers to memory controlled by the same chip select.
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*
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* the eeprom contents are defined as in technical note #2 - basically,
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* a header, zero or more records in no particular order, and a 32 bit crc
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* a record is 1 or more type bytes, a length byte and "length" bytes.
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*/
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#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */
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#define HYMOD_EEPROM_VER 1 /* eeprom contents version */
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#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */
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/* eeprom header */
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typedef
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struct {
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unsigned char id; /* eeprom id byte */
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unsigned char ver; /* eeprom contents version number */
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unsigned long len; /* total # of bytes btw hdr and crc */
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}
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hymod_eehdr_t;
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/* maximum number of bytes available for eeprom data records */
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#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \
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- sizeof (hymod_eehdr_t) \
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- sizeof (unsigned long))
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/* eeprom data record */
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typedef
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union {
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struct {
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unsigned char topbit:1;
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unsigned char type:7;
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unsigned char len;
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unsigned char data[1]; /* variable length */
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} small;
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struct {
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unsigned short topbit:1;
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unsigned short nxtbit:1;
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unsigned short type:14;
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unsigned short len;
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unsigned char data[1]; /* variable length */
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} medium;
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struct {
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unsigned long topbit:1;
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unsigned long nxtbit:1;
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unsigned long type:30;
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unsigned long len;
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unsigned char data[1]; /* variable length */
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} large;
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}
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hymod_eerec_t;
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#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */
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#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */
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/* eeprom record types */
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#define HYMOD_EEREC_SERNO 1 /* serial number */
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#define HYMOD_EEREC_DATE 2 /* date */
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#define HYMOD_EEREC_BATCH 3 /* batch id */
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#define HYMOD_EEREC_TYPE 4 /* board type */
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#define HYMOD_EEREC_REV 5 /* revision number */
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#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */
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#define HYMOD_EEREC_FLASH 7 /* flash sizes */
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#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */
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#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */
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#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */
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#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */
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#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */
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#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */
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#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */
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#define HYMOD_EEREC_BUSSPD 15 /* bus speed */
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#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */
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#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */
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#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */
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#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */
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/* some dimensions */
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#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */
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#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */
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#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */
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#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */
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#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */
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#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */
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/* board types */
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#define HYMOD_BDTYPE_NONE 0 /* information not present */
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#define HYMOD_BDTYPE_IO 1 /* I/O main board */
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#define HYMOD_BDTYPE_CLP 2 /* CLP main board */
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#define HYMOD_BDTYPE_DSP 3 /* DSP main board */
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#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */
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#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */
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#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */
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#define HYMOD_BDTYPE_MAX 7 /* first invalid value */
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/* Xilinx fpga types */
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#define HYMOD_XTYP_NONE 0 /* information not present */
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#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */
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#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */
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#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */
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#define HYMOD_XTYP_MAX 4 /* first invalid value */
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/* Xilinx fpga speeds */
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#define HYMOD_XSPD_NONE 0 /* information not present */
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#define HYMOD_XSPD_SIX 1
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#define HYMOD_XSPD_SEVEN 2
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#define HYMOD_XSPD_EIGHT 3
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#define HYMOD_XSPD_MAX 4 /* first invalid value */
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/* Xilinx fpga temperatures */
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#define HYMOD_XTMP_NONE 0 /* information not present */
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#define HYMOD_XTMP_COM 1
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#define HYMOD_XTMP_IND 2
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#define HYMOD_XTMP_MAX 3 /* first invalid value */
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/* Xilinx fpga grades */
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#define HYMOD_XTMP_NONE 0 /* information not present */
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#define HYMOD_XTMP_NORMAL 1
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#define HYMOD_XTMP_ENGSAMP 2
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#define HYMOD_XTMP_MAX 3 /* first invalid value */
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/* CPU types */
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#define HYMOD_CPUTYPE_NONE 0 /* information not present */
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#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */
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#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */
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/* CPU/BUS/CPM clock speeds */
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#define HYMOD_CLKSPD_NONE 0 /* information not present */
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#define HYMOD_CLKSPD_33MHZ 1
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#define HYMOD_CLKSPD_66MHZ 2
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#define HYMOD_CLKSPD_100MHZ 3
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#define HYMOD_CLKSPD_133MHZ 4
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#define HYMOD_CLKSPD_166MHZ 5
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#define HYMOD_CLKSPD_200MHZ 6
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#define HYMOD_CLKSPD_MAX 7 /* first invalid value */
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/* high speed serial chip types */
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#define HYMOD_HSSTYPE_NONE 0 /* information not present */
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#define HYMOD_HSSTYPE_AMCC52064 1
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#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */
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/* a date (yyyy-mm-dd) */
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typedef
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struct {
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unsigned short year;
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unsigned char month;
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unsigned char day;
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}
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hymod_date_t;
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/* describes a Xilinx fpga */
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typedef
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struct {
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unsigned char type; /* chip type */
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unsigned char speed; /* chip speed rating */
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unsigned char temp; /* chip temperature rating */
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unsigned char grade; /* chip grade */
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}
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hymod_xlx_t;
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/* describes a Motorola embedded processor */
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typedef
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struct {
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unsigned char type; /* CPU type */
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unsigned char cpuspd; /* speed of the PowerPC core */
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unsigned char busspd; /* speed of the system and 60x bus */
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unsigned char cpmspd; /* speed of the CPM co-processor */
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}
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hymod_mpc_t;
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/* info about high-speed (1Gbit) serial interface */
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typedef
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struct {
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unsigned char type; /* high-speed serial chip type */
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unsigned char nchin; /* number of input channels mounted */
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unsigned char nchout; /* number of output channels mounted */
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}
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hymod_hss_t;
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/*
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* this defines the contents of the serial eeprom that exists on every
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* hymod board, including mezzanine boards (the serial eeprom will be
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* faked for early development boards that don't have one)
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*/
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typedef
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struct {
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unsigned char ver; /* eeprom contents version */
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unsigned char bdtype; /* board type */
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unsigned char bdrev; /* board revision */
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unsigned char batchlen; /* length of batch string below */
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unsigned long serno; /* serial number */
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hymod_date_t date; /* manufacture date */
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unsigned char batch[32]; /* manufacturer specific batch id */
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unsigned char nsdram; /* # of ram "banks" */
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unsigned char nflash; /* # of flash "banks" */
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unsigned char nzbt; /* # of ZBT rams */
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unsigned char nxlx; /* # of Xilinx fpgas */
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unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */
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unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */
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unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */
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hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */
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hymod_mpc_t mpc; /* Motorola MPC CPU info */
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hymod_hss_t hss; /* high-speed serial info */
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}
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hymod_eeprom_t;
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/*
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* this defines a region in the processor's physical address space
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*/
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typedef
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struct {
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unsigned long exists:1; /* 1 if the region exists, 0 if not */
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unsigned long size:31; /* size in bytes */
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unsigned long base; /* base address */
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}
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xlx_prgn_t;
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/*
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* this defines where the various Xilinx fpga access regions are mapped
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* into the physical address space of the processor
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*/
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typedef
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struct {
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xlx_prgn_t prog; /* program access region */
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xlx_prgn_t reg; /* register access region */
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xlx_prgn_t port; /* port access region */
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}
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xlx_mmap_t;
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/*
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* this defines which 8260 i/o port pins are connected to the various
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* signals required for programming a Xilinx fpga
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*/
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typedef
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struct {
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iopin_t prog_pin; /* assert for >= 300ns to program */
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iopin_t init_pin; /* goes high when fpga is cleared */
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iopin_t done_pin; /* goes high when program is done */
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iopin_t enable_pin; /* some fpgas need enabling */
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}
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xlx_iopins_t;
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/* all info about one hymod board */
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typedef
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struct {
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unsigned char eeprom_valid:1;
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hymod_eeprom_t eeprom;
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xlx_mmap_t mmap[HYMOD_MAX_XLX];
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xlx_iopins_t iopins[HYMOD_MAX_XLX];
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}
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hymod_board_t;
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/*
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* this defines the configuration information of a hymod board-set
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* (main board + possible mezzanine board). In future, there may be
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* more than one mezzanine board (stackable?) - if so, add a "mezz2"
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* field, and so on... or make mezz an array?
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*/
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typedef
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struct {
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hymod_board_t main; /* main board info */
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hymod_board_t mezz; /* mezzanine board info */
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unsigned long crc; /* ensures kernel and boot prom agree */
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}
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hymod_conf_t;
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#endif /* _ASM_HYMOD_H_ */
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