upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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181 lines
7.8 KiB
181 lines
7.8 KiB
22 years ago
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/*
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* (C) Copyright 2003
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* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* File: mpc5xx.h
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*
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* Discription: mpc5xx specific definitions
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*
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*/
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#ifndef __MPC5XX_H__
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#define __MPC5XX_H__
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/*-----------------------------------------------------------------------
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* Exception offsets (PowerPC standard)
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*/
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#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
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/*-----------------------------------------------------------------------
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* ISB bit in IMMR to set internal memory map
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*/
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#define CFG_ISB ((CFG_IMMR / 0x00400000) << 1)
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control Register
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*/
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#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
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#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
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#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
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#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
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#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
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#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
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#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration Register
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*/
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#define SIUMCR_EARB 0x80000000 /* External Arbitration */
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#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
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#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
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#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
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#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
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#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
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#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
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#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
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#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
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#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
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#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
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#define SIUMCR_DBGC01 0x00200000 /* - " - */
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#define SIUMCR_DBGC10 0x00400000 /* - " - */
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#define SIUMCR_DBGC11 0x00600000 /* - " - */
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#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
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#define SIUMCR_DBPC01 0x00080000 /* - " - */
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#define SIUMCR_DBPC10 0x00100000 /* - " - */
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#define SIUMCR_DBPC11 0x00180000 /* - " - */
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#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
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#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
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#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
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#define SIUMCR_SC10 0x00004000 /* Single adress show */
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#define SIUMCR_SC11 0x00006000 /* Single adress */
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#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */
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#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
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#define SIUMCR_MLRC01 0x00000400 /* - " - */
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#define SIUMCR_MLRC10 0x00000800 /* - " - */
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#define SIUMCR_MLRC11 0x00000c00 /* - " - */
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#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control Register
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*/
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#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */
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#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */
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#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control Register
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*/
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#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register
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*/
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#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */
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#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */
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#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */
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#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
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#define PLPRCR_DIVF_0 0x00900000 /* Division factor 0 */
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#define PLPRCR_MF_9 0x00000000 /* Mulitipliaction factor 9 */
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#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
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#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
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#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register
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*/
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#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
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#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
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#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
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#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
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#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
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#define SCCR_EBDF11 0x00060000 /* reserved */
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#define SCCR_TBS 0x02000000 /* Time Base Source */
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#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
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#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
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#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
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#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
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/*-----------------------------------------------------------------------
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* MC - Memory Controller
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*/
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#define BR_V 0x00000001 /* Bank valid */
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#define BR_BI 0x00000002 /* Burst inhibit */
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#define BR_PS_8 0x00000400 /* 8 bit port size */
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#define BR_PS_16 0x00000800 /* 16 bit port size */
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#define BR_PS_32 0x00000000 /* 32 bit port size */
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#define BR_LBDIR 0x00000008 /* Late burst data in progess */
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#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
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#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */
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#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */
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#define OR_TRLX 0x00000001 /* Timing relaxed */
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#define OR_BSCY 0x00000060 /* Burst beats length in clocks */
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#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */
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#define OR_CSNT 0x00000800 /* Chip-select negotation time */
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#define OR_ETHR 0x00000000 /* Extended hold time on read */
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#define OR_ADDR_MK_FF 0xFF000000
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#define OR_ADDR_MK_FFFF 0xFFFF0000
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/*-----------------------------------------------------------------------
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* UMCR - UIMB Module Configuration Register
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*/
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#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
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#define UMCR_HSPEED 0x10000000 /* Half speed */
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/*-----------------------------------------------------------------------
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* ICTRL - I-Bus Support Control Register
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*/
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#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */
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#define NR_IRQS 0 /* Place this later in a separate file */
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/*-----------------------------------------------------------------------
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* SCI - Serial communication interface
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*/
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#define SCI_TDRE 0x0100 /* Transmit data register empty */
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#define SCI_TE 0x0008 /* Transmitter enabled */
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#define SCI_RE 0x0004 /* Receiver enabled */
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#define SCI_RDRF 0x0040 /* Receive data register full */
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#define SCI_PE 0x0400 /* Parity enable */
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#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
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#define SCI_SCXDR_MK 0x00ff /* Data register mask */
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#define SCI_M_11 0x0200 /* Frame size is 11 bit */
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#define SCI_M_10 0x0000 /* Frame size is 10 bit */
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#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
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#define SCI_PORT_2 ((int)2)
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#endif /* __MPC5XX_H__ */
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