upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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448 lines
15 KiB
448 lines
15 KiB
20 years ago
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/*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003,Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <ioports.h>
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#include <spd.h>
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#include <miiphy.h>
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#if defined(CONFIG_DDR_ECC)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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extern long int spd_sdram(void);
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void local_bus_init(void);
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long int fixed_sdram(void);
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
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/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
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/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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int board_early_init_f (void)
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{
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return 0;
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}
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void reset_phy (void)
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{
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}
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int checkboard (void)
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{
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puts("Board: MicroSys PM856\n");
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#ifdef CONFIG_PCI
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printf(" PCI1: 32 bit, %d MHz (compiled)\n",
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CONFIG_SYS_CLK_FREQ / 1000000);
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#else
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printf(" PCI1: disabled\n");
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#endif
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/*
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* Initialize local bus.
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*/
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local_bus_init();
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return 0;
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}
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long int
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initdram(int board_type)
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{
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long dram_size = 0;
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extern long spd_sdram (void);
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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{
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volatile ccsr_gur_t *gur= &immap->im_gur;
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int i,x;
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x = 10;
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/*
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* Work around to stabilize DDR DLL
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*/
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gur->ddrdllcr = 0x81000000;
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asm("sync;isync;msync");
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udelay (200);
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while (gur->ddrdllcr != 0x81000100)
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{
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gur->devdisr = gur->devdisr | 0x00010000;
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asm("sync;isync;msync");
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for (i=0; i<x; i++)
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;
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gur->devdisr = gur->devdisr & 0xfff7ffff;
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asm("sync;isync;msync");
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x++;
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}
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}
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#endif
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram ();
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#else
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dram_size = fixed_sdram ();
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#endif
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#if defined(CONFIG_DDR_ECC)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
||
|
|
|
||
|
|
uint clkdiv;
|
||
|
|
uint lbc_hz;
|
||
|
|
sys_info_t sysinfo;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Errata LBC11.
|
||
|
|
* Fix Local Bus clock glitch when DLL is enabled.
|
||
|
|
*
|
||
|
|
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
|
||
|
|
* If localbus freq is > 133Mhz, DLL can be safely enabled.
|
||
|
|
* Between 66 and 133, the DLL is enabled with an override workaround.
|
||
|
|
*/
|
||
|
|
|
||
|
|
get_sys_info(&sysinfo);
|
||
|
|
clkdiv = lbc->lcrr & 0x0f;
|
||
|
|
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
|
||
|
|
|
||
|
|
if (lbc_hz < 66) {
|
||
|
|
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
|
||
|
|
|
||
|
|
} else if (lbc_hz >= 133) {
|
||
|
|
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
|
||
|
|
|
||
|
|
} else {
|
||
|
|
/*
|
||
|
|
* On REV1 boards, need to change CLKDIV before enable DLL.
|
||
|
|
* Default CLKDIV is 8, change it to 4 temporarily.
|
||
|
|
*/
|
||
|
|
uint pvr = get_pvr();
|
||
|
|
uint temp_lbcdll = 0;
|
||
|
|
|
||
|
|
if (pvr == PVR_85xx_REV1) {
|
||
|
|
/* FIXME: Justify the high bit here. */
|
||
|
|
lbc->lcrr = 0x10000004;
|
||
|
|
}
|
||
|
|
|
||
|
|
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
|
||
|
|
udelay(200);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Sample LBC DLL ctrl reg, upshift it to set the
|
||
|
|
* override bits.
|
||
|
|
*/
|
||
|
|
temp_lbcdll = gur->lbcdllcr;
|
||
|
|
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
|
||
|
|
asm("sync;isync;msync");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(CFG_DRAM_TEST)
|
||
|
|
int testdram (void)
|
||
|
|
{
|
||
|
|
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||
|
|
uint *pend = (uint *) CFG_MEMTEST_END;
|
||
|
|
uint *p;
|
||
|
|
|
||
|
|
printf("SDRAM test phase 1:\n");
|
||
|
|
for (p = pstart; p < pend; p++)
|
||
|
|
*p = 0xaaaaaaaa;
|
||
|
|
|
||
|
|
for (p = pstart; p < pend; p++) {
|
||
|
|
if (*p != 0xaaaaaaaa) {
|
||
|
|
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
printf("SDRAM test phase 2:\n");
|
||
|
|
for (p = pstart; p < pend; p++)
|
||
|
|
*p = 0x55555555;
|
||
|
|
|
||
|
|
for (p = pstart; p < pend; p++) {
|
||
|
|
if (*p != 0x55555555) {
|
||
|
|
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
printf("SDRAM test passed.\n");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#if !defined(CONFIG_SPD_EEPROM)
|
||
|
|
/*************************************************************************
|
||
|
|
* fixed sdram init -- doesn't use serial presence detect.
|
||
|
|
************************************************************************/
|
||
|
|
long int fixed_sdram (void)
|
||
|
|
{
|
||
|
|
#ifndef CFG_RAMBOOT
|
||
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||
|
|
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
||
|
|
|
||
|
|
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||
|
|
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||
|
|
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
|
||
|
|
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
|
||
|
|
ddr->sdram_mode = CFG_DDR_MODE;
|
||
|
|
ddr->sdram_interval = CFG_DDR_INTERVAL;
|
||
|
|
#if defined (CONFIG_DDR_ECC)
|
||
|
|
ddr->err_disable = 0x0000000D;
|
||
|
|
ddr->err_sbe = 0x00ff0000;
|
||
|
|
#endif
|
||
|
|
asm("sync;isync;msync");
|
||
|
|
udelay(500);
|
||
|
|
#if defined (CONFIG_DDR_ECC)
|
||
|
|
/* Enable ECC checking */
|
||
|
|
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
|
||
|
|
#else
|
||
|
|
ddr->sdram_cfg = CFG_DDR_CONTROL;
|
||
|
|
#endif
|
||
|
|
asm("sync; isync; msync");
|
||
|
|
udelay(500);
|
||
|
|
#endif
|
||
|
|
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||
|
|
}
|
||
|
|
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(CONFIG_PCI)
|
||
|
|
/*
|
||
|
|
* Initialize PCI Devices, report devices found.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifndef CONFIG_PCI_PNP
|
||
|
|
static struct pci_config_table pci_mpc85xxads_config_table[] = {
|
||
|
|
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||
|
|
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||
|
|
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||
|
|
PCI_ENET0_MEMADDR,
|
||
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
||
|
|
} },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
static struct pci_controller hose = {
|
||
|
|
#ifndef CONFIG_PCI_PNP
|
||
|
|
config_table: pci_mpc85xxads_config_table,
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* CONFIG_PCI */
|
||
|
|
|
||
|
|
|
||
|
|
void
|
||
|
|
pci_init_board(void)
|
||
|
|
{
|
||
|
|
#ifdef CONFIG_PCI
|
||
|
|
pci_mpc85xx_init(&hose);
|
||
|
|
#endif /* CONFIG_PCI */
|
||
|
|
}
|