upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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120 lines
2.9 KiB
120 lines
2.9 KiB
20 years ago
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/*
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* (C) Copyright 2004, Freescale, Inc
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* TsiChung Liew, Tsi-Chung.Liew@freescale.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8220.h>
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#include <asm/processor.h>
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typedef struct pllmultiplier {
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u8 hid1;
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int multi;
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int vco_div;
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} pllcfg_t;
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/* ------------------------------------------------------------------------- */
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/*
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*
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*/
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int get_clocks (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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pllcfg_t bus2core[] = {
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{0x10, 2, 8}, /* 1 */
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{0x08, 2, 4},
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{0x60, 3, 8}, /* 1.5 */
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{0x00, 3, 4},
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{0xc0, 3, 2},
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{0x28, 4, 4}, /* 2 */
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{0x20, 4, 2},
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{0x88, 5, 4}, /* 2.5 */
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{0x30, 5, 2},
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{0x80, 6, 4}, /* 3 */
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{0x40, 6, 2},
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{0x70, 7, 2}, /* 3.5 */
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{0x50, 8, 2}, /* 4 */
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{0x38, 9, 2}, /* 4.5 */
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{0x58, 10, 2}, /* 5 */
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{0x48, 11, 2}, /* 5.5 */
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{0x68, 12, 2}, /* 6 */
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{0x90, 13, 2}, /* 6.5 */
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{0xa0, 14, 2}, /* 7 */
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{0xb0, 15, 2}, /* 7.5 */
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{0xe0, 16, 2} /* 8 */
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};
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u32 hid1;
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int i, size;
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#if !defined(CFG_MPC8220_CLKIN)
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#error clock measuring not implemented yet - define CFG_MPC8220_CLKIN
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#endif
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gd->inp_clk = CFG_MPC8220_CLKIN;
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/* Bus clock is fixed at 120Mhz for now */
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/* will do dynamic in the future */
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gd->bus_clk = CFG_MPC8220_CLKIN * 4;
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/* PCI clock is same as input clock */
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gd->pci_clk = CFG_MPC8220_CLKIN;
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/* FlexBus is temporary set as the same as input clock */
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/* will do dynamic in the future */
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gd->flb_clk = CFG_MPC8220_CLKIN;
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/* CPU Clock - Read HID1 */
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asm volatile ("mfspr %0, 1009":"=r" (hid1):);
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size = sizeof (bus2core) / sizeof (pllcfg_t);
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hid1 >>= 24;
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for (i = 0; i < size; i++)
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if (hid1 == bus2core[i].hid1) {
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gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
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/* Input Multiplier is determined by MPLL,
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hardcoded for now at 16 */
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gd->vco_clk = gd->pci_clk * 16;
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break;
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}
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/* hardcoded 81MHz for now */
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gd->pev_clk = 81000000;
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return (0);
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}
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int prt_mpc8220_clks (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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printf (" Bus %ld MHz, CPU %ld MHz, PCI %ld MHz, VCO %ld MHz\n",
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gd->bus_clk / 1000000, gd->cpu_clk / 1000000,
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gd->pci_clk / 1000000, gd->vco_clk / 1000000);
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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