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AMCC Ocotea Board
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Last Update: March 2, 2004
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=======================================================================
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This file contains some handy info regarding U-Boot and the AMCC
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Ocotea 440gx evaluation board. See the README.ppc440 for additional
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information.
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SWITCH SETTINGS & JUMPERS
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==========================
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Here's what I've been using successfully. If you feel inclined to
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change things ... please read the docs!
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DIPSW U46 U80
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------------------------
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SW 1 off off
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SW 2 on off
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SW 3 off off
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SW 4 off off
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SW 5 off off
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SW 6 on on
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SW 7 on off
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SW 8 on off
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J41: strapped
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J42: open
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All others are factory default.
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I2C Information
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=====================
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See README.ebony for information.
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PCI
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===========================
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Untested at the time of writing.
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PPC440GX Ethernet EMACs
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===========================
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All EMAC ports have been tested and are known to work
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with EPS Group 4.
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Special note about the Cicada CIS8201:
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The CIS8201 Gigabit PHY comes up in GMII mode by default.
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One must hit an extended register to allow use of RGMII mode.
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This has been done in the 440gx_enet.c file with a #ifdef/endif
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pair.
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AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
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The addresses contained in the config header file are from my particular
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board and you _*should*_ change them to reflect your board either in the
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config file and/or in your environment variables. I found the addresses on
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labels on the bottom side of the board.
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BDI2k or JTAG Debugging
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===========================
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For ease of debugging you can swap the small boot flash and external SRAM
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by changing U46:3 to on. You can then use the sram as your boot flash by
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loading the sram via the jtag debugger.
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Regards,
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--Travis
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<tsawyer@sandburst.com>
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