upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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64 lines
2.4 KiB
64 lines
2.4 KiB
21 years ago
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/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __NIOS2_H__
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#define __NIOS2_H__
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/*------------------------------------------------------------------------
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* Control registers -- use with wrctl() & rdctl()
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*----------------------------------------------------------------------*/
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#define CTL_STATUS 0 /* Processor status reg */
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#define CTL_ESTATUS 1 /* Exception status reg */
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#define CTL_BSTATUS 2 /* Break status reg */
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#define CTL_IENABLE 3 /* Interrut enable reg */
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#define CTL_IPENDING 4 /* Interrut pending reg */
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/*------------------------------------------------------------------------
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* Access to control regs
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*----------------------------------------------------------------------*/
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#define _str_(x) #x
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#define rdctl(reg)\
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({unsigned int val;\
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asm volatile( "rdctl %0, ctl" _str_(reg)\
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: "=r" (val) ); val;})
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#define wrctl(reg,val)\
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asm volatile( "wrctl ctl" _str_(reg) ",%0"\
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: : "r" (val))
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/*------------------------------------------------------------------------
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* Control reg bit masks
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*----------------------------------------------------------------------*/
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#define STATUS_IE (1<<0) /* Interrupt enable */
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#define STATUS_U (1<<1) /* User-mode */
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/*------------------------------------------------------------------------
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* Bit-31 Cache bypass -- only valid for data access. When data cache
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* is not implemented, bit 31 is ignored for compatibility.
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*----------------------------------------------------------------------*/
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#define CACHE_BYPASS(a) ((a) | 0x80000000)
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#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
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#endif /* __NIOS2_H__ */
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