upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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93 lines
3.0 KiB
93 lines
3.0 KiB
17 years ago
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/*
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* Configuation settings for MPR2
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*
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* Copyright (C) 2008
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* Mark Jonas <mark.jonas@de.bosch.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MPR2_H
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#define __MPR2_H
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/* Supported commands */
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_FLASH
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/* Default environment variables */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS "console=ttySC0,115200"
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#define CONFIG_BOOTFILE /boot/zImage
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#define CONFIG_LOADADDR 0x8E000000
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#define CONFIG_VERSION_VARIABLE
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/* CPU and platform */
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#define CONFIG_SH 1
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#define CONFIG_SH3 1
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#define CONFIG_CPU_SH7720 1
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#define CONFIG_MPR2 1
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/* U-Boot internals */
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
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#define CFG_PBSIZE 256 /* Buffer size for Console output */
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#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
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#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
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#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
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#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (128 * 1024)
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#define CFG_MALLOC_LEN (256 * 1024)
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#define CFG_GBL_DATA_SIZE 256
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/* Memory */
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#define CFG_SDRAM_BASE 0x8C000000
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#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
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#define CFG_MEMTEST_START CFG_SDRAM_BASE
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#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
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/* Flash */
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_FLASH_BASE 0xA0000000
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE (128 * 1024)
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#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_FLASH_ERASE_TOUT 120000
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#define CFG_FLASH_WRITE_TOUT 500
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/* Clocks */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
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#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
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/* UART */
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#define CFG_SCIF_CONSOLE 1
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#define CONFIG_CONS_SCIF0 1
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#endif /* __MPR2_H */
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