upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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75 lines
1.8 KiB
75 lines
1.8 KiB
23 years ago
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/*
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* Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <command.h>
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#include <mpc8xx.h>
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#include <version.h>
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#define CONFIG_8xx 1 /* needed for Linux kernel header files */
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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/*
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* cache flushing routines for kgdb
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*/
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.globl kgdb_flush_cache_all
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kgdb_flush_cache_all:
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lis r3, IDC_INVALL@h
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mtspr DC_CST, r3
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sync
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lis r3, IDC_INVALL@h
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mtspr IC_CST, r3
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SYNC
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blr
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.globl kgdb_flush_cache_range
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kgdb_flush_cache_range:
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li r5,CFG_CACHELINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,CFG_CACHELINE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,CFG_CACHELINE_SIZE
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,CFG_CACHELINE_SIZE
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bdnz 2b
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SYNC
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blr
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#endif /* CFG_CMD_KGDB */
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