upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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176 lines
4.8 KiB
176 lines
4.8 KiB
14 years ago
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/*
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* Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
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*
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* Copyright (C) 2010 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _SDMMC_DEFS_H_
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#define _SDMMC_DEFS_H_
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#include <asm/arch/hardware.h>
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/* MMC Control Reg fields */
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#define MMCCTL_DATRST (1 << 0)
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#define MMCCTL_CMDRST (1 << 1)
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#define MMCCTL_WIDTH_4_BIT (1 << 2)
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#define MMCCTL_DATEG_DISABLED (0 << 6)
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#define MMCCTL_DATEG_RISING (1 << 6)
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#define MMCCTL_DATEG_FALLING (2 << 6)
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#define MMCCTL_DATEG_BOTH (3 << 6)
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#define MMCCTL_PERMDR_LE (0 << 9)
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#define MMCCTL_PERMDR_BE (1 << 9)
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#define MMCCTL_PERMDX_LE (0 << 10)
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#define MMCCTL_PERMDX_BE (1 << 10)
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/* MMC Clock Control Reg fields */
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#define MMCCLK_CLKEN (1 << 8)
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#define MMCCLK_CLKRT_MASK (0xFF << 0)
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/* MMC Status Reg0 fields */
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#define MMCST0_DATDNE (1 << 0)
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#define MMCST0_BSYDNE (1 << 1)
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#define MMCST0_RSPDNE (1 << 2)
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#define MMCST0_TOUTRD (1 << 3)
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#define MMCST0_TOUTRS (1 << 4)
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#define MMCST0_CRCWR (1 << 5)
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#define MMCST0_CRCRD (1 << 6)
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#define MMCST0_CRCRS (1 << 7)
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#define MMCST0_DXRDY (1 << 9)
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#define MMCST0_DRRDY (1 << 10)
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#define MMCST0_DATED (1 << 11)
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#define MMCST0_TRNDNE (1 << 12)
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#define MMCST0_ERR_MASK (0x00F8)
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/* MMC Status Reg1 fields */
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#define MMCST1_BUSY (1 << 0)
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#define MMCST1_CLKSTP (1 << 1)
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#define MMCST1_DXEMP (1 << 2)
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#define MMCST1_DRFUL (1 << 3)
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#define MMCST1_DAT3ST (1 << 4)
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#define MMCST1_FIFOEMP (1 << 5)
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#define MMCST1_FIFOFUL (1 << 6)
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/* MMC INT Mask Reg fields */
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#define MMCIM_EDATDNE (1 << 0)
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#define MMCIM_EBSYDNE (1 << 1)
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#define MMCIM_ERSPDNE (1 << 2)
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#define MMCIM_ETOUTRD (1 << 3)
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#define MMCIM_ETOUTRS (1 << 4)
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#define MMCIM_ECRCWR (1 << 5)
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#define MMCIM_ECRCRD (1 << 6)
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#define MMCIM_ECRCRS (1 << 7)
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#define MMCIM_EDXRDY (1 << 9)
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#define MMCIM_EDRRDY (1 << 10)
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#define MMCIM_EDATED (1 << 11)
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#define MMCIM_ETRNDNE (1 << 12)
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#define MMCIM_MASKALL (0xFFFFFFFF)
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/* MMC Resp Tout Reg fields */
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#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
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#define MMCTOR_TOD_20_16_SHIFT (8)
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/* MMC Data Read Tout Reg fields */
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#define MMCTOD_TOD_0_15_MASK (0xFFFF)
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/* MMC Block len Reg fields */
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#define MMCBLEN_BLEN_MASK (0xFFF)
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/* MMC Num Blocks Reg fields */
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#define MMCNBLK_NBLK_MASK (0xFFFF)
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#define MMCNBLK_NBLK_MAX (0xFFFF)
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/* MMC Num Blocks Counter Reg fields */
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#define MMCNBLC_NBLC_MASK (0xFFFF)
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/* MMC Cmd Reg fields */
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#define MMCCMD_CMD_MASK (0x3F)
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#define MMCCMD_PPLEN (1 << 7)
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#define MMCCMD_BSYEXP (1 << 8)
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#define MMCCMD_RSPFMT_NONE (0 << 9)
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#define MMCCMD_RSPFMT_R1567 (1 << 9)
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#define MMCCMD_RSPFMT_R2 (2 << 9)
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#define MMCCMD_RSPFMT_R3 (3 << 9)
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#define MMCCMD_DTRW (1 << 11)
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#define MMCCMD_STRMTP (1 << 12)
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#define MMCCMD_WDATX (1 << 13)
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#define MMCCMD_INITCK (1 << 14)
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#define MMCCMD_DCLR (1 << 15)
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#define MMCCMD_DMATRIG (1 << 16)
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/* FIFO control Reg fields */
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#define MMCFIFOCTL_FIFORST (1 << 0)
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#define MMCFIFOCTL_FIFODIR (1 << 1)
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#define MMCFIFOCTL_FIFOLEV (1 << 2)
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#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
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#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
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#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
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#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
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/* Davinci MMC Register definitions */
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struct davinci_mmc_regs {
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dv_reg mmcctl;
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dv_reg mmcclk;
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dv_reg mmcst0;
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dv_reg mmcst1;
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dv_reg mmcim;
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dv_reg mmctor;
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dv_reg mmctod;
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dv_reg mmcblen;
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dv_reg mmcnblk;
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dv_reg mmcnblc;
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dv_reg mmcdrr;
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dv_reg mmcdxr;
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dv_reg mmccmd;
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dv_reg mmcarghl;
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dv_reg mmcrsp01;
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dv_reg mmcrsp23;
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dv_reg mmcrsp45;
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dv_reg mmcrsp67;
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dv_reg mmcdrsp;
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dv_reg mmcetok;
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dv_reg mmccidx;
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dv_reg mmcckc;
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dv_reg mmctorc;
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dv_reg mmctodc;
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dv_reg mmcblnc;
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dv_reg sdioctl;
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dv_reg sdiost0;
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dv_reg sdioien;
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dv_reg sdioist;
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dv_reg mmcfifoctl;
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};
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/* Davinci MMC board definitions */
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struct davinci_mmc {
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struct davinci_mmc_regs *reg_base; /* Register base address */
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uint input_clk; /* Input clock to MMC controller */
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uint host_caps; /* Host capabilities */
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uint voltages; /* Host supported voltages */
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uint version; /* MMC Controller version */
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};
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enum {
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MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
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MMC_CTLR_VERSION_2, /* DA830 */
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};
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int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
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#endif /* _SDMMC_DEFS_H */
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