upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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174 lines
5.9 KiB
174 lines
5.9 KiB
15 years ago
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/*
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* TNETV107X: Hardware information
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#ifndef __ASSEMBLY__
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#include <asm/sizes.h>
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#define ASYNC_EMIF_NUM_CS 4
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#define ASYNC_EMIF_MODE_NOR 0
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#define ASYNC_EMIF_MODE_NAND 1
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#define ASYNC_EMIF_MODE_ONENAND 2
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#define ASYNC_EMIF_PRESERVE -1
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struct async_emif_config {
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unsigned mode;
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unsigned select_strobe;
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unsigned extend_wait;
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unsigned wr_setup;
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unsigned wr_strobe;
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unsigned wr_hold;
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unsigned rd_setup;
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unsigned rd_strobe;
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unsigned rd_hold;
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unsigned turn_around;
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enum {
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ASYNC_EMIF_8 = 0,
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ASYNC_EMIF_16 = 1,
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ASYNC_EMIF_32 = 2,
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} width;
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};
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void init_async_emif(int num_cs, struct async_emif_config *config);
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int wdt_start(unsigned long msecs);
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int wdt_stop(void);
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int wdt_kick(void);
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#endif
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/* Chip configuration unlock codes and registers */
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#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
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#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
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#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
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#define TNETV107X_KICK0_MAGIC 0x83e70b13
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#define TNETV107X_KICK1_MAGIC 0x95a4f1e0
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/* Module base addresses */
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#define TNETV107X_TPCC_BASE 0x01C00000
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#define TNETV107X_TPTC0_BASE 0x01C10000
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#define TNETV107X_TPTC1_BASE 0x01C10400
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#define TNETV107X_INTC_BASE 0x03000000
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#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
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#define TNETV107X_INTD_BASE 0x08038000
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#define TNETV107X_INTD_IPC_BASE 0x08038000
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#define TNETV107X_INTD_FAST_BASE 0x08039000
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#define TNETV107X_INTD_ASYNC_BASE 0x0803A000
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#define TNETV107X_INTD_SLOW_BASE 0x0803B000
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#define TNETV107X_PKA_BASE 0x08040000
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#define TNETV107X_RNG_BASE 0x08044000
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#define TNETV107X_TIMER0_BASE 0x08086500
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#define TNETV107X_TIMER1_BASE 0x08086600
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#define TNETV107X_WDT0_ARM_BASE 0x08086700
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#define TNETV107X_WDT1_DSP_BASE 0x08086800
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#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
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#define TNETV107X_GPIO_BASE 0x08088000
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#define TNETV107X_UART1_BASE 0x08088400
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#define TNETV107X_TOUCHSCREEN_BASE 0x08088500
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#define TNETV107X_SDIO0_BASE 0x08088700
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#define TNETV107X_SDIO1_BASE 0x08088800
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#define TNETV107X_MDIO_BASE 0x08088900
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#define TNETV107X_KEYPAD_BASE 0x08088A00
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#define TNETV107X_SSP_BASE 0x08088C00
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#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
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#define TNETV107X_PSC_BASE 0x0808B000
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#define TNETV107X_TDM0_BASE 0x08100000
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#define TNETV107X_TDM1_BASE 0x08100100
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#define TNETV107X_MCDMA_BASE 0x08108000
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#define TNETV107X_UART0_DMA_BASE 0x08108200
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#define TNETV107X_USBSS_BASE 0x08120000
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#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
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#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
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#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
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#define TNETV107X_IMCOP_BASE 0x01CC0000
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#define TNETV107X_MBX_LITE_BASE 0x07000000
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#define TNETV107X_ETHSS_BASE 0x0803C000
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#define TNETV107X_CPSW_BASE 0x0803C000
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#define TNETV107X_SPF_BASE 0x0803C800
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#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
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#define TNETV107X_VTP_CNTRL_0 0x0803D800
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#define TNETV107X_VTP_CNTRL_1 0x0803D900
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#define TNETV107X_UART2_DMA_BASE 0x08108400
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#define TNETV107X_INTERNAL_MEMORY 0x20000000
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#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
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#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
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#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
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#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
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#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
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#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
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/* LPSC module definitions */
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#define TNETV107X_LPSC_ARM 0
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#define TNETV107X_LPSC_GEM 1
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#define TNETV107X_LPSC_DDR2_PHY 2
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#define TNETV107X_LPSC_TPCC 3
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#define TNETV107X_LPSC_TPTC0 4
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#define TNETV107X_LPSC_TPTC1 5
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#define TNETV107X_LPSC_RAM 6
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#define TNETV107X_LPSC_MBX_LITE 7
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#define TNETV107X_LPSC_LCD 8
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#define TNETV107X_LPSC_ETHSS 9
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#define TNETV107X_LPSC_AEMIF 10
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#define TNETV107X_LPSC_CHIP_CFG 11
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#define TNETV107X_LPSC_TSC 12
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#define TNETV107X_LPSC_ROM 13
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#define TNETV107X_LPSC_UART2 14
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#define TNETV107X_LPSC_PKTSEC 15
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#define TNETV107X_LPSC_SECCTL 16
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#define TNETV107X_LPSC_KEYMGR 17
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#define TNETV107X_LPSC_KEYPAD 18
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#define TNETV107X_LPSC_GPIO 19
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#define TNETV107X_LPSC_MDIO 20
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#define TNETV107X_LPSC_SDIO0 21
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#define TNETV107X_LPSC_UART0 22
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#define TNETV107X_LPSC_UART1 23
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#define TNETV107X_LPSC_TIMER0 24
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#define TNETV107X_LPSC_TIMER1 25
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#define TNETV107X_LPSC_WDT_ARM 26
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#define TNETV107X_LPSC_WDT_DSP 27
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#define TNETV107X_LPSC_SSP 28
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#define TNETV107X_LPSC_TDM0 29
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#define TNETV107X_LPSC_VLYNQ 30
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#define TNETV107X_LPSC_MCDMA 31
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#define TNETV107X_LPSC_USB0 32
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#define TNETV107X_LPSC_TDM1 33
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#define TNETV107X_LPSC_DEBUGSS 34
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#define TNETV107X_LPSC_ETHSS_RGMII 35
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#define TNETV107X_LPSC_SYSTEM 36
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#define TNETV107X_LPSC_IMCOP 37
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#define TNETV107X_LPSC_SPARE 38
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#define TNETV107X_LPSC_SDIO1 39
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#define TNETV107X_LPSC_USB1 40
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#define TNETV107X_LPSC_USBSS 41
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#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
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#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
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#define TNETV107X_LPSC_MAX 44
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/* Interrupt controller */
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#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
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#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
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#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
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#endif /* __ASM_ARCH_HARDWARE_H */
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