upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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138 lines
4.6 KiB
138 lines
4.6 KiB
19 years ago
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/*
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* U-boot bf533_irq.h
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*
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* Copyright (c) 2005 blackfin.uclinux.org
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*
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* This file is based on
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* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
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* Changed by HuTao Apr18, 2003
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*
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* Copyright was missing when I got the code so took from MIPS arch ...MaTed---
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* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
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* Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
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*
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* Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
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* Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
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* Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
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*
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* Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
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* Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _BF533_IRQ_H_
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#define _BF533_IRQ_H_
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/*
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* Interrupt source definitions
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* Event Source Core Event Name Number
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* EMU 0
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* Reset RST 1
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* NMI NMI 2
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* Exception EVX 3
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* Reserved -- 4
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* Hardware Error IVHW 5
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* Core Timer IVTMR 6
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* PLL Wakeup Interrupt IVG7 7
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* DMA Error (generic) IVG7 8
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* PPI Error Interrupt IVG7 9
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* SPORT0 Error Interrupt IVG7 10
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* SPORT1 Error Interrupt IVG7 11
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* SPI Error Interrupt IVG7 12
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* UART Error Interrupt IVG7 13
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* RTC Interrupt IVG8 14
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* DMA0 Interrupt (PPI) IVG8 15
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* DMA1 (SPORT0 RX) IVG9 16
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* DMA2 (SPORT0 TX) IVG9 17
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* DMA3 (SPORT1 RX) IVG9 18
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* DMA4 (SPORT1 TX) IVG9 19
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* DMA5 (PPI) IVG10 20
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* DMA6 (UART RX) IVG10 21
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* DMA7 (UART TX) IVG10 22
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* Timer0 IVG11 23
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* Timer1 IVG11 24
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* Timer2 IVG11 25
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* PF Interrupt A IVG12 26
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* PF Interrupt B IVG12 27
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* DMA8/9 Interrupt IVG13 28
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* DMA10/11 Interrupt IVG13 29
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* Watchdog Timer IVG13 30
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* Software Interrupt 1 IVG14 31
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* Software Interrupt 2 --
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* (lowest priority) IVG15 32
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*/
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/* The ABSTRACT IRQ definitions */
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19 years ago
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/* The first seven of the following are fixed,
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19 years ago
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* the rest you change if you need to
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*/
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#define IRQ_EMU 0 /* Emulation */
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#define IRQ_RST 1 /* reset */
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#define IRQ_NMI 2 /* Non Maskable */
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#define IRQ_EVX 3 /* Exception */
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#define IRQ_UNUSED 4 /* - unused interrupt */
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#define IRQ_HWERR 5 /* Hardware Error */
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#define IRQ_CORETMR 6 /* Core timer */
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#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
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#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
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#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
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#define IRQ_UART_ERROR 13 /* UART Error Interrupt */
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#define IRQ_RTC 14 /* RTC Interrupt */
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#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */
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#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */
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#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */
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#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
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#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */
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#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */
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#define IRQ_TMR0 23 /* Timer 0 */
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#define IRQ_TMR1 24 /* Timer 1 */
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#define IRQ_TMR2 25 /* Timer 2 */
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#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
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#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
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#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
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#define IRQ_WATCH 30 /* Watch Dog Timer */
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#define IRQ_SW_INT1 31 /* Software Int 1 */
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#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */
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#define IRQ_UART_RX_BIT 0x4000
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#define IRQ_UART_TX_BIT 0x8000
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#define IRQ_UART_ERROR_BIT 0x40
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#define IVG7 7
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#define IVG8 8
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#define IVG9 9
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#define IVG10 10
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#define IVG11 11
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#define IVG12 12
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#define IVG13 13
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#define IVG14 14
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#define IVG15 15
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#define SYS_IRQS 33
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#endif
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