upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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96 lines
2.9 KiB
96 lines
2.9 KiB
16 years ago
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/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __EBI__
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#define __EBI__
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#include <common.h>
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#include <asm/io.h>
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#include "vct.h"
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#define EXT_DEVICE_CHANNEL_3 (0x30000000)
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#define EXT_DEVICE_CHANNEL_2 (0x20000000)
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#define EXT_DEVICE_CHANNEL_1 (0x10000000)
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#define EXT_CPU_ACCESS_ACTIVE (0x00000001)
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#define EXT_DMA_ACCESS_ACTIVE (1 << 14)
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#define EXT_CPU_IORDY_SL (0x00000001)
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#define EBI_CPU_WRITE (1 << 31)
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#define EBI_CPU_ID_SHIFT (28)
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#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT)
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/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
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#define ADDR_LATCH_ENABLE 0
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#define ADDR_ACTIVATION 4
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#define CHIP_SELECT_START 8
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#define OUTPUT_ENABLE_START 12
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#define WAIT_TIME 28
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#define READ_DURATION 20
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/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
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#define OUTPUT_ENABLE_END 0
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#define CHIP_SELECT_END 4
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#define ADDR_DEACTIVATION 8
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#define RECOVER_TIME 12
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#define ACK_TIME 20
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/* various bits in configuration register EBI_DEV[01]_CONFIG1 */
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#define EBI_EXTERNAL_DATA_8 (1 << 8)
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#define EBI_EXT_ADDR_SHIFT (1 << 22)
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#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT
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#define EBI_CHIP_SELECT_1 0x2
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#define EBI_CHIP_SELECT_2 0x4
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#define EBI_BUSY_EN_RD (1 << 12)
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#define DIR_ACCESS_WRITE (1 << 20)
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#define DIR_ACCESS_MASK (1 << 20)
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/* various bits in configuration register EBI_DEV[01]_CONFIG2 */
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#define ADDRESS_INCREMENT_ON 0x0
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#define ADDRESS_INCREMENT_OFF 0x100
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#define QUEUE_LENGTH_1 0x40
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#define QUEUE_LENGTH_2 0x80
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#define QUEUE_LENGTH_3 0xC0
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#define QUEUE_LENGTH_4 0
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#define CPU_TRANSFER_SIZE_32 0
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#define CPU_TRANSFER_SIZE_16 0x10
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#define CPU_TRANSFER_SIZE_8 0x20
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#define READ_ENDIANNESS_ABCD 0
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#define READ_ENDIANNESS_DCBA 0x4
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#define READ_ENDIANNESS_BADC 0x8
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#define READ_ENDIANNESS_CDAB 0xC
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#define WRITE_ENDIANNESS_ABCD 0
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#define WRITE_ENDIANNESS_DCBA 0x1
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#define WRITE_ENDIANNESS_BADC 0x2
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#define WRITE_ENDIANNESS_CDAB 0x3
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/* various bits in configuration register EBI_CTRL_SIG_ACTLV */
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#define IORDY_ACTIVELEVEL_HIGH (1 << 14)
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#define ALE_ACTIVELEVEL_HIGH (1 << 8)
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/* bits in register EBI_SIG_LEVEL */
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#define IORDY_LEVEL_MASK 1
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static inline void ebi_wait(void)
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{
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while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
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; /* wait */
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}
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#endif
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