upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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286 lines
6.9 KiB
286 lines
6.9 KiB
16 years ago
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CLOCKS_OMAP3_H_
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#define _CLOCKS_OMAP3_H_
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#define PLL_STOP 1 /* PER & IVA */
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#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
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#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
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#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
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/*
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* The following configurations are OPP and SysClk value independant
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* and hence are defined here. All the other DPLL related values are
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* tabulated in lowlevel_init.S.
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*/
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/* CORE DPLL */
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#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
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#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
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#define CORE_FUSB_DIV 2 /* 41.5MHz: */
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#define CORE_L4_DIV 2 /* 83MHz : L4 */
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#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
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#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
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#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
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/* PER DPLL */
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#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
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#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
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#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
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#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
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#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
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/* MPU DPLL */
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#define MPU_M_12_ES1 0x0FE
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#define MPU_N_12_ES1 0x07
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#define MPU_FSEL_12_ES1 0x05
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#define MPU_M2_12_ES1 0x01
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#define MPU_M_12_ES2 0x0FA
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#define MPU_N_12_ES2 0x05
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#define MPU_FSEL_12_ES2 0x07
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#define MPU_M2_ES2 0x01
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#define MPU_M_12 0x085
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#define MPU_N_12 0x05
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#define MPU_FSEL_12 0x07
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#define MPU_M2_12 0x01
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#define MPU_M_13_ES1 0x17D
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#define MPU_N_13_ES1 0x0C
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#define MPU_FSEL_13_ES1 0x03
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#define MPU_M2_13_ES1 0x01
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#define MPU_M_13_ES2 0x1F4
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#define MPU_N_13_ES2 0x0C
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#define MPU_FSEL_13_ES2 0x03
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#define MPU_M2_13_ES2 0x01
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#define MPU_M_13 0x10A
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#define MPU_N_13 0x0C
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#define MPU_FSEL_13 0x03
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#define MPU_M2_13 0x01
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#define MPU_M_19P2_ES1 0x179
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#define MPU_N_19P2_ES1 0x12
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#define MPU_FSEL_19P2_ES1 0x04
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#define MPU_M2_19P2_ES1 0x01
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#define MPU_M_19P2_ES2 0x271
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#define MPU_N_19P2_ES2 0x17
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#define MPU_FSEL_19P2_ES2 0x03
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#define MPU_M2_19P2_ES2 0x01
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#define MPU_M_19P2 0x14C
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#define MPU_N_19P2 0x17
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#define MPU_FSEL_19P2 0x03
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#define MPU_M2_19P2 0x01
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#define MPU_M_26_ES1 0x17D
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#define MPU_N_26_ES1 0x19
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#define MPU_FSEL_26_ES1 0x03
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#define MPU_M2_26_ES1 0x01
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#define MPU_M_26_ES2 0x0FA
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#define MPU_N_26_ES2 0x0C
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#define MPU_FSEL_26_ES2 0x07
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#define MPU_M2_26_ES2 0x01
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#define MPU_M_26 0x085
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#define MPU_N_26 0x0C
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#define MPU_FSEL_26 0x07
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#define MPU_M2_26 0x01
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#define MPU_M_38P4_ES1 0x1FA
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#define MPU_N_38P4_ES1 0x32
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#define MPU_FSEL_38P4_ES1 0x03
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#define MPU_M2_38P4_ES1 0x01
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#define MPU_M_38P4_ES2 0x271
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#define MPU_N_38P4_ES2 0x2F
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#define MPU_FSEL_38P4_ES2 0x03
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#define MPU_M2_38P4_ES2 0x01
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#define MPU_M_38P4 0x14C
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#define MPU_N_38P4 0x2F
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#define MPU_FSEL_38P4 0x03
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#define MPU_M2_38P4 0x01
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/* IVA DPLL */
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#define IVA_M_12_ES1 0x07D
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#define IVA_N_12_ES1 0x05
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#define IVA_FSEL_12_ES1 0x07
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#define IVA_M2_12_ES1 0x01
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#define IVA_M_12_ES2 0x0B4
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#define IVA_N_12_ES2 0x05
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#define IVA_FSEL_12_ES2 0x07
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#define IVA_M2_12_ES2 0x01
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#define IVA_M_12 0x085
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#define IVA_N_12 0x05
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#define IVA_FSEL_12 0x07
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#define IVA_M2_12 0x01
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#define IVA_M_13_ES1 0x0FA
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#define IVA_N_13_ES1 0x0C
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#define IVA_FSEL_13_ES1 0x03
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#define IVA_M2_13_ES1 0x01
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#define IVA_M_13_ES2 0x168
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#define IVA_N_13_ES2 0x0C
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#define IVA_FSEL_13_ES2 0x03
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#define IVA_M2_13_ES2 0x01
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#define IVA_M_13 0x10A
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#define IVA_N_13 0x0C
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#define IVA_FSEL_13 0x03
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#define IVA_M2_13 0x01
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#define IVA_M_19P2_ES1 0x082
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#define IVA_N_19P2_ES1 0x09
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#define IVA_FSEL_19P2_ES1 0x07
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#define IVA_M2_19P2_ES1 0x01
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#define IVA_M_19P2_ES2 0x0E1
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#define IVA_N_19P2_ES2 0x0B
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#define IVA_FSEL_19P2_ES2 0x06
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#define IVA_M2_19P2_ES2 0x01
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#define IVA_M_19P2 0x14C
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#define IVA_N_19P2 0x17
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#define IVA_FSEL_19P2 0x03
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#define IVA_M2_19P2 0x01
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#define IVA_M_26_ES1 0x07D
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#define IVA_N_26_ES1 0x0C
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#define IVA_FSEL_26_ES1 0x07
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#define IVA_M2_26_ES1 0x01
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#define IVA_M_26_ES2 0x0B4
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#define IVA_N_26_ES2 0x0C
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#define IVA_FSEL_26_ES2 0x07
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#define IVA_M2_26_ES2 0x01
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#define IVA_M_26 0x085
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#define IVA_N_26 0x0C
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#define IVA_FSEL_26 0x07
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#define IVA_M2_26 0x01
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#define IVA_M_38P4_ES1 0x13F
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#define IVA_N_38P4_ES1 0x30
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#define IVA_FSEL_38P4_ES1 0x03
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#define IVA_M2_38P4_ES1 0x01
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#define IVA_M_38P4_ES2 0x0E1
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#define IVA_N_38P4_ES2 0x17
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#define IVA_FSEL_38P4_ES2 0x06
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#define IVA_M2_38P4_ES2 0x01
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#define IVA_M_38P4 0x14C
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#define IVA_N_38P4 0x2F
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#define IVA_FSEL_38P4 0x03
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#define IVA_M2_38P4 0x01
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/* CORE DPLL */
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#define CORE_M_12 0xA6
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#define CORE_N_12 0x05
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#define CORE_FSEL_12 0x07
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#define CORE_M2_12 0x01 /* M3 of 2 */
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#define CORE_M_12_ES1 0x19F
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#define CORE_N_12_ES1 0x0E
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#define CORE_FSL_12_ES1 0x03
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#define CORE_M2_12_ES1 0x1 /* M3 of 2 */
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#define CORE_M_13 0x14C
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#define CORE_N_13 0x0C
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#define CORE_FSEL_13 0x03
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#define CORE_M2_13 0x01 /* M3 of 2 */
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#define CORE_M_13_ES1 0x1B2
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#define CORE_N_13_ES1 0x10
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#define CORE_FSL_13_ES1 0x03
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#define CORE_M2_13_ES1 0x01 /* M3 of 2 */
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#define CORE_M_19P2 0x19F
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#define CORE_N_19P2 0x17
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#define CORE_FSEL_19P2 0x03
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#define CORE_M2_19P2 0x01 /* M3 of 2 */
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#define CORE_M_19P2_ES1 0x19F
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#define CORE_N_19P2_ES1 0x17
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#define CORE_FSL_19P2_ES1 0x03
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#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
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#define CORE_M_26 0xA6
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#define CORE_N_26 0x0C
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#define CORE_FSEL_26 0x07
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#define CORE_M2_26 0x01 /* M3 of 2 */
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#define CORE_M_26_ES1 0x1B2
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#define CORE_N_26_ES1 0x21
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#define CORE_FSL_26_ES1 0x03
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#define CORE_M2_26_ES1 0x01 /* M3 of 2 */
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#define CORE_M_38P4 0x19F
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#define CORE_N_38P4 0x2F
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#define CORE_FSEL_38P4 0x03
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#define CORE_M2_38P4 0x01 /* M3 of 2 */
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#define CORE_M_38P4_ES1 0x19F
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#define CORE_N_38P4_ES1 0x2F
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#define CORE_FSL_38P4_ES1 0x03
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#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
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/* PER DPLL */
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#define PER_M_12 0xD8
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#define PER_N_12 0x05
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#define PER_FSEL_12 0x07
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#define PER_M2_12 0x09
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#define PER_M_13 0x1B0
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#define PER_N_13 0x0C
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#define PER_FSEL_13 0x03
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#define PER_M2_13 0x09
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#define PER_M_19P2 0xE1
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#define PER_N_19P2 0x09
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#define PER_FSEL_19P2 0x07
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#define PER_M2_19P2 0x09
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#define PER_M_26 0xD8
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#define PER_N_26 0x0C
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#define PER_FSEL_26 0x07
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#define PER_M2_26 0x09
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#define PER_M_38P4 0xE1
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#define PER_N_38P4 0x13
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#define PER_FSEL_38P4 0x07
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#define PER_M2_38P4 0x09
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#endif /* endif _CLOCKS_OMAP3_H_ */
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