upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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928 lines
25 KiB
928 lines
25 KiB
19 years ago
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/**
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* @file IxQMgrAqmIf_p.h
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*
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* @author Intel Corporation
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* @date 30-Oct-2001
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*
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* @brief The IxQMgrAqmIf sub-component provides a number of inline
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* functions for performing I/O on the AQM.
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*
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* Because some functions contained in this module are inline and are
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* used in other modules (within the QMgr component) the definitions are
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* contained in this header file. The "normal" use of inline functions
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* is to use the inline functions in the module in which they are
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* defined. In this case these inline functions are used in external
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* modules and therefore the use of "inline extern". What this means
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* is as follows: if a function foo is declared as "inline extern"this
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* definition is only used for inlining, in no case is the function
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* compiled on its own. If the compiler cannot inline the function it
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* becomes an external reference. Therefore in IxQMgrAqmIf.c all
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* inline functions are defined without the "inline extern" specifier
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* and so define the external references. In all other modules these
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* funtions are defined as "inline extern".
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IXQMGRAQMIF_P_H
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#define IXQMGRAQMIF_P_H
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#include "IxOsalTypes.h"
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/*
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* inline definition
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*/
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#ifdef IX_OSAL_INLINE_ALL
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/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
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inline functions */
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#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
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#else
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#ifdef IXQMGRAQMIF_C
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#ifndef IX_QMGR_AQMIF_INLINE
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#define IX_QMGR_AQMIF_INLINE
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#endif
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#else
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#ifndef IX_QMGR_AQMIF_INLINE
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#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
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#endif
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#endif /* IXQMGRAQMIF_C */
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#endif /* IX_OSAL_INLINE */
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/*
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* User defined include files.
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*/
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#include "IxQMgr.h"
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#include "IxQMgrLog_p.h"
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#include "IxQMgrQCfg_p.h"
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/* Because this file contains inline functions which will be compiled into
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* other components, we need to ensure that the IX_COMPONENT_NAME define
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* is set to ix_qmgr while this code is being compiled. This will ensure
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* that the correct implementation is provided for the memory access macros
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* IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
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* This must be done before including "IxOsalMemAccess.h"
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*/
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#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
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#undef IX_COMPONENT_NAME
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#define IX_COMPONENT_NAME ix_qmgr
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#include "IxOsal.h"
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/*
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* #defines and macros used in this file.
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*/
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/* Number of bytes per word */
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#define IX_QMGR_NUM_BYTES_PER_WORD 4
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/* Underflow bit mask */
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#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0
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/* Overflow bit mask */
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#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1
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/* Queue access register, queue 0 */
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#define IX_QMGR_QUEACC0_OFFSET 0x0000
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/* Size of queue access register in words */
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#define IX_QMGR_QUEACC_SIZE 0x4/*words*/
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/* Queue status register, queues 0-7 */
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#define IX_QMGR_QUELOWSTAT0_OFFSET (IX_QMGR_QUEACC0_OFFSET +\
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(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
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/* Queue status register, queues 8-15 */
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#define IX_QMGR_QUELOWSTAT1_OFFSET (IX_QMGR_QUELOWSTAT0_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue status register, queues 16-23 */
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#define IX_QMGR_QUELOWSTAT2_OFFSET (IX_QMGR_QUELOWSTAT1_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue status register, queues 24-31 */
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#define IX_QMGR_QUELOWSTAT3_OFFSET (IX_QMGR_QUELOWSTAT2_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue status register Q status bits mask */
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#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
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/* Size of queue 0-31 status register */
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#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/
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/* The number of queues' status specified per word */
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#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
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/* Queue UF/OF status register queues 0-15 */
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#define IX_QMGR_QUEUOSTAT0_OFFSET (IX_QMGR_QUELOWSTAT3_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue UF/OF status register queues 16-31 */
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#define IX_QMGR_QUEUOSTAT1_OFFSET (IX_QMGR_QUEUOSTAT0_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* The number of queues' underflow/overflow status specified per word */
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#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
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/* Queue NE status register, queues 32-63 */
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#define IX_QMGR_QUEUPPSTAT0_OFFSET (IX_QMGR_QUEUOSTAT1_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue F status register, queues 32-63 */
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#define IX_QMGR_QUEUPPSTAT1_OFFSET (IX_QMGR_QUEUPPSTAT0_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Size of queue 32-63 status register */
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#define IX_QMGR_QUEUPPSTAT_SIZE 0x2 /*words*/
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/* The number of queues' status specified per word */
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#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
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/* Queue INT source select register, queues 0-7 */
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#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue INT source select register, queues 8-15 */
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#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue INT source select register, queues 16-23 */
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#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue INT source select register, queues 24-31 */
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#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Size of interrupt source select reegister */
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#define IX_QMGR_INT0SRCSELREG_SIZE 0x4 /*words*/
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/* The number of queues' interrupt source select specified per word*/
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#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
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/* Queue INT enable register, queues 0-31 */
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#define IX_QMGR_QUEIEREG0_OFFSET (IX_QMGR_INT0SRCSELREG3_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue INT enable register, queues 32-63 */
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#define IX_QMGR_QUEIEREG1_OFFSET (IX_QMGR_QUEIEREG0_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Queue INT register, queues 0-31 */
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#define IX_QMGR_QINTREG0_OFFSET (IX_QMGR_QUEIEREG1_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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||
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/* Queue INT register, queues 32-63 */
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#define IX_QMGR_QINTREG1_OFFSET (IX_QMGR_QINTREG0_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD)
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/* Size of interrupt register */
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#define IX_QMGR_QINTREG_SIZE 0x2 /*words*/
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/* Number of queues' status specified per word */
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#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
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/* Number of bits per queue interrupt status */
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#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
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#define IX_QMGR_QINTREG_BIT_OFFSET 0x1
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/* Size of address space not used by AQM */
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#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES 0x1bC0
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/* Queue config register, queue 0 */
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#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
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IX_QMGR_NUM_BYTES_PER_WORD +\
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IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
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/* Total size of configuration words */
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||
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#define IX_QMGR_QUECONFIG_SIZE 0x100
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/* Start of SRAM queue buffer space */
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||
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#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
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IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
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/* Total bits in a word */
|
||
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#define BITS_PER_WORD 32
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||
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||
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/* Size of queue buffer space */
|
||
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#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
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||
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/*
|
||
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* This macro will return the address of the access register for the
|
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* queue specified by qId
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||
|
|
*/
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||
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#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
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(((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
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||
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+ IX_QMGR_QUEACC0_OFFSET)
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||
|
|
|
||
|
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/*
|
||
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* Bit location of bit-3 of INT0SRCSELREG0 register to enabled
|
||
|
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* sticky interrupt register.
|
||
|
|
*/
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||
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#define IX_QMGR_INT0SRCSELREG0_BIT3 3
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||
|
|
|
||
|
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/*
|
||
|
|
* Variable declerations global to this file. Externs are followed by
|
||
|
|
* statics.
|
||
|
|
*/
|
||
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extern UINT32 aqmBaseAddress;
|
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|
|
|
||
|
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/*
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||
|
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* Function declarations.
|
||
|
|
*/
|
||
|
|
void
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||
|
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ixQMgrAqmIfInit (void);
|
||
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|
||
|
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void
|
||
|
|
ixQMgrAqmIfUninit (void);
|
||
|
|
|
||
|
|
unsigned
|
||
|
|
ixQMgrAqmIfLog2 (unsigned number);
|
||
|
|
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId,
|
||
|
|
UINT32 registerBaseAddrOffset,
|
||
|
|
unsigned queuesPerRegWord,
|
||
|
|
UINT32 value);
|
||
|
|
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
|
||
|
|
IxQMgrSourceId srcSel,
|
||
|
|
unsigned int *statusWordOffset,
|
||
|
|
UINT32 *checkValue,
|
||
|
|
UINT32 *mask);
|
||
|
|
/*
|
||
|
|
* The Xscale software allways deals with logical addresses and so the
|
||
|
|
* base address of the AQM memory space is not a hardcoded value. This
|
||
|
|
* function must be called before any other function in this component.
|
||
|
|
* NO CHECKING is performed to ensure that the base address has been
|
||
|
|
* set.
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfBaseAddressSet (UINT32 address);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Get the base address of the AQM memory space.
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfBaseAddressGet (UINT32 *address);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Get the sram base address
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Read a queue status
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
|
||
|
|
IxQMgrQStatus* status);
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set INT0SRCSELREG0 Bit3
|
||
|
|
*/
|
||
|
|
void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set the interrupt source
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
|
||
|
|
IxQMgrSourceId sourceId);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable interruptson a queue
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Disable interrupt on a quee
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Write the config register of the specified queue
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
|
||
|
|
IxQMgrQSizeInWords qSizeInWords,
|
||
|
|
IxQMgrQEntrySizeInWords entrySizeInWords,
|
||
|
|
UINT32 freeSRAMAddress);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* read fields from the config of the specified queue.
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
|
||
|
|
unsigned int numEntries,
|
||
|
|
UINT32 *baseAddress,
|
||
|
|
unsigned int *ne,
|
||
|
|
unsigned int *nf,
|
||
|
|
UINT32 *readPtr,
|
||
|
|
UINT32 *writePtr);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set the ne and nf watermark level on a queue.
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
|
||
|
|
unsigned ne,
|
||
|
|
unsigned nf);
|
||
|
|
|
||
|
|
/* Inspect an entry without moving the read pointer */
|
||
|
|
IX_STATUS
|
||
|
|
ixQMgrAqmIfQPeek (IxQMgrQId qId,
|
||
|
|
unsigned int entryIndex,
|
||
|
|
unsigned int *entry);
|
||
|
|
|
||
|
|
/* Modify an entry without moving the write pointer */
|
||
|
|
IX_STATUS
|
||
|
|
ixQMgrAqmIfQPoke (IxQMgrQId qId,
|
||
|
|
unsigned int entryIndex,
|
||
|
|
unsigned int *entry);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Function prototype for inline functions. For description refers to
|
||
|
|
* the functions defintion below.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfWordWrite (VUINT32 *address,
|
||
|
|
UINT32 word);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfWordRead (VUINT32 *address,
|
||
|
|
UINT32 *word);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQPop (IxQMgrQId qId,
|
||
|
|
IxQMgrQEntrySizeInWords numWords,
|
||
|
|
UINT32 *entry);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQPush (IxQMgrQId qId,
|
||
|
|
IxQMgrQEntrySizeInWords numWords,
|
||
|
|
UINT32 *entry);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 *qStatusWords);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
|
||
|
|
UINT32 *newQStatusWords,
|
||
|
|
unsigned int statusWordOffset,
|
||
|
|
UINT32 checkValue,
|
||
|
|
UINT32 mask);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
|
||
|
|
UINT32 registerBaseAddrOffset,
|
||
|
|
unsigned queuesPerRegWord,
|
||
|
|
unsigned relativeBitOffset,
|
||
|
|
BOOL reset);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE UINT32
|
||
|
|
ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
|
||
|
|
UINT32 registerBaseAddrOffset,
|
||
|
|
unsigned queuesPerRegWord);
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 reg);
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 *regVal);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
|
||
|
|
IxQMgrQStatus *status);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
|
||
|
|
IxQMgrQStatus *status);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
|
||
|
|
IxQMgrQStatus *qStatus);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE unsigned
|
||
|
|
ixQMgrAqmIfPow2NumDivide (unsigned numerator,
|
||
|
|
unsigned denominator);
|
||
|
|
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 *regVal);
|
||
|
|
/*
|
||
|
|
* Inline functions
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This inline function is used by other QMgr components to write one
|
||
|
|
* word to the specified address.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfWordWrite (VUINT32 *address,
|
||
|
|
UINT32 word)
|
||
|
|
{
|
||
|
|
IX_OSAL_WRITE_LONG(address, word);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This inline function is used by other QMgr components to read a
|
||
|
|
* word from the specified address.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfWordRead (VUINT32 *address,
|
||
|
|
UINT32 *word)
|
||
|
|
{
|
||
|
|
*word = IX_OSAL_READ_LONG(address);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This inline function is used by other QMgr components to pop an
|
||
|
|
* entry off the specified queue.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQPop (IxQMgrQId qId,
|
||
|
|
IxQMgrQEntrySizeInWords numWords,
|
||
|
|
UINT32 *entry)
|
||
|
|
{
|
||
|
|
volatile UINT32 *accRegAddr;
|
||
|
|
|
||
|
|
accRegAddr = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_Q_ACCESS_ADDR_GET(qId));
|
||
|
|
|
||
|
|
switch (numWords)
|
||
|
|
{
|
||
|
|
case IX_QMGR_Q_ENTRY_SIZE1:
|
||
|
|
ixQMgrAqmIfWordRead (accRegAddr, entry);
|
||
|
|
break;
|
||
|
|
case IX_QMGR_Q_ENTRY_SIZE2:
|
||
|
|
ixQMgrAqmIfWordRead (accRegAddr++, entry++);
|
||
|
|
ixQMgrAqmIfWordRead (accRegAddr, entry);
|
||
|
|
break;
|
||
|
|
case IX_QMGR_Q_ENTRY_SIZE4:
|
||
|
|
ixQMgrAqmIfWordRead (accRegAddr++, entry++);
|
||
|
|
ixQMgrAqmIfWordRead (accRegAddr++, entry++);
|
||
|
|
ixQMgrAqmIfWordRead (accRegAddr++, entry++);
|
||
|
|
ixQMgrAqmIfWordRead (accRegAddr, entry);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This inline function is used by other QMgr components to push an
|
||
|
|
* entry to the specified queue.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQPush (IxQMgrQId qId,
|
||
|
|
IxQMgrQEntrySizeInWords numWords,
|
||
|
|
UINT32 *entry)
|
||
|
|
{
|
||
|
|
volatile UINT32 *accRegAddr;
|
||
|
|
|
||
|
|
accRegAddr = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_Q_ACCESS_ADDR_GET(qId));
|
||
|
|
|
||
|
|
switch (numWords)
|
||
|
|
{
|
||
|
|
case IX_QMGR_Q_ENTRY_SIZE1:
|
||
|
|
ixQMgrAqmIfWordWrite (accRegAddr, *entry);
|
||
|
|
break;
|
||
|
|
case IX_QMGR_Q_ENTRY_SIZE2:
|
||
|
|
ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
|
||
|
|
ixQMgrAqmIfWordWrite (accRegAddr, *entry);
|
||
|
|
break;
|
||
|
|
case IX_QMGR_Q_ENTRY_SIZE4:
|
||
|
|
ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
|
||
|
|
ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
|
||
|
|
ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
|
||
|
|
ixQMgrAqmIfWordWrite (accRegAddr, *entry);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The AQM interrupt registers contains a bit for each AQM queue
|
||
|
|
* specifying the queue (s) that cause an interrupt to fire. This
|
||
|
|
* function is called by IxQMGrDispatcher component.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 *qStatusWords)
|
||
|
|
{
|
||
|
|
volatile UINT32 *regAddress = NULL;
|
||
|
|
|
||
|
|
if (group == IX_QMGR_QUELOW_GROUP)
|
||
|
|
{
|
||
|
|
regAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QUELOWSTAT0_OFFSET);
|
||
|
|
|
||
|
|
ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
|
||
|
|
ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
|
||
|
|
ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
|
||
|
|
ixQMgrAqmIfWordRead (regAddress, qStatusWords);
|
||
|
|
}
|
||
|
|
else /* We have the upper queues */
|
||
|
|
{
|
||
|
|
/* Only need to read the Nearly Empty status register for
|
||
|
|
* queues 32-63 as for therse queues the interrtupt source
|
||
|
|
* condition is fixed to Nearly Empty
|
||
|
|
*/
|
||
|
|
regAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QUEUPPSTAT0_OFFSET);
|
||
|
|
ixQMgrAqmIfWordRead (regAddress, qStatusWords);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This function check if the status for a queue has changed between
|
||
|
|
* 2 snapshots and if it has, that the status matches a particular
|
||
|
|
* value after masking.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
|
||
|
|
UINT32 *newQStatusWords,
|
||
|
|
unsigned int statusWordOffset,
|
||
|
|
UINT32 checkValue,
|
||
|
|
UINT32 mask)
|
||
|
|
{
|
||
|
|
if (((oldQStatusWords[statusWordOffset] & mask) !=
|
||
|
|
(newQStatusWords[statusWordOffset] & mask)) &&
|
||
|
|
((newQStatusWords[statusWordOffset] & mask) == checkValue))
|
||
|
|
{
|
||
|
|
return TRUE;
|
||
|
|
}
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The AQM interrupt register contains a bit for each AQM queue
|
||
|
|
* specifying the queue (s) that cause an interrupt to fire. This
|
||
|
|
* function is called by IxQMgrDispatcher component.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 *regVal)
|
||
|
|
{
|
||
|
|
volatile UINT32 *regAddress;
|
||
|
|
|
||
|
|
if (group == IX_QMGR_QUELOW_GROUP)
|
||
|
|
{
|
||
|
|
regAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QINTREG0_OFFSET);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
regAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QINTREG1_OFFSET);
|
||
|
|
}
|
||
|
|
|
||
|
|
ixQMgrAqmIfWordRead (regAddress, regVal);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The AQM interrupt enable register contains a bit for each AQM queue.
|
||
|
|
* This function reads the interrupt enable register. This
|
||
|
|
* function is called by IxQMgrDispatcher component.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 *regVal)
|
||
|
|
{
|
||
|
|
volatile UINT32 *regAddress;
|
||
|
|
|
||
|
|
if (group == IX_QMGR_QUELOW_GROUP)
|
||
|
|
{
|
||
|
|
regAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QUEIEREG0_OFFSET);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
regAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QUEIEREG1_OFFSET);
|
||
|
|
}
|
||
|
|
|
||
|
|
ixQMgrAqmIfWordRead (regAddress, regVal);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This inline function will read the status bit of a queue
|
||
|
|
* specified by qId. If reset is TRUE the bit is cleared.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
|
||
|
|
UINT32 registerBaseAddrOffset,
|
||
|
|
unsigned queuesPerRegWord,
|
||
|
|
unsigned relativeBitOffset,
|
||
|
|
BOOL reset)
|
||
|
|
{
|
||
|
|
UINT32 actualBitOffset;
|
||
|
|
volatile UINT32 *registerAddress;
|
||
|
|
UINT32 registerWord;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Calculate the registerAddress
|
||
|
|
* multiple queues split accross registers
|
||
|
|
*/
|
||
|
|
registerAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
registerBaseAddrOffset +
|
||
|
|
((qId / queuesPerRegWord) *
|
||
|
|
IX_QMGR_NUM_BYTES_PER_WORD));
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Get the status word
|
||
|
|
*/
|
||
|
|
ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Calculate the actualBitOffset
|
||
|
|
* status for multiple queues stored in one register
|
||
|
|
*/
|
||
|
|
actualBitOffset = (relativeBitOffset + 1) <<
|
||
|
|
((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
|
||
|
|
|
||
|
|
/* Check if the status bit is set */
|
||
|
|
if (registerWord & actualBitOffset)
|
||
|
|
{
|
||
|
|
/* Clear the bit if reset */
|
||
|
|
if (reset)
|
||
|
|
{
|
||
|
|
ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
|
||
|
|
}
|
||
|
|
return TRUE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Bit not set */
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* @ingroup IxQmgrAqmIfAPI
|
||
|
|
*
|
||
|
|
* @brief Read the underflow status of a queue
|
||
|
|
*
|
||
|
|
* This inline function will read the underflow status of a queue
|
||
|
|
* specified by qId.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
|
||
|
|
{
|
||
|
|
if (qId < IX_QMGR_MIN_QUEUPP_QID)
|
||
|
|
{
|
||
|
|
return (ixQMgrAqmIfRegisterBitCheck (qId,
|
||
|
|
IX_QMGR_QUEUOSTAT0_OFFSET,
|
||
|
|
IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
|
||
|
|
IX_QMGR_UNDERFLOW_BIT_OFFSET,
|
||
|
|
TRUE/*reset*/));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Qs 32-63 have no underflow status */
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This inline function will read the overflow status of a queue
|
||
|
|
* specified by qId.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE BOOL
|
||
|
|
ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
|
||
|
|
{
|
||
|
|
if (qId < IX_QMGR_MIN_QUEUPP_QID)
|
||
|
|
{
|
||
|
|
return (ixQMgrAqmIfRegisterBitCheck (qId,
|
||
|
|
IX_QMGR_QUEUOSTAT0_OFFSET,
|
||
|
|
IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
|
||
|
|
IX_QMGR_OVERFLOW_BIT_OFFSET,
|
||
|
|
TRUE/*reset*/));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Qs 32-63 have no overflow status */
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This inline function will read the status bits of a queue
|
||
|
|
* specified by qId.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE UINT32
|
||
|
|
ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
|
||
|
|
UINT32 registerBaseAddrOffset,
|
||
|
|
unsigned queuesPerRegWord)
|
||
|
|
{
|
||
|
|
volatile UINT32 *registerAddress;
|
||
|
|
UINT32 registerWord;
|
||
|
|
UINT32 statusBitsMask;
|
||
|
|
UINT32 bitsPerQueue;
|
||
|
|
|
||
|
|
bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Calculate the registerAddress
|
||
|
|
* multiple queues split accross registers
|
||
|
|
*/
|
||
|
|
registerAddress = (UINT32*)(aqmBaseAddress +
|
||
|
|
registerBaseAddrOffset +
|
||
|
|
((qId / queuesPerRegWord) *
|
||
|
|
IX_QMGR_NUM_BYTES_PER_WORD));
|
||
|
|
/*
|
||
|
|
* Read the status word
|
||
|
|
*/
|
||
|
|
ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Calculate the mask for the status bits for this queue.
|
||
|
|
*/
|
||
|
|
statusBitsMask = ((1 << bitsPerQueue) - 1);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Shift the status word so it is right justified
|
||
|
|
*/
|
||
|
|
registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Mask out all bar the status bits for this queue
|
||
|
|
*/
|
||
|
|
return (registerWord &= statusBitsMask);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This function is called by IxQMgrDispatcher to set the contents of
|
||
|
|
* the AQM interrupt register.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
|
||
|
|
UINT32 reg)
|
||
|
|
{
|
||
|
|
volatile UINT32 *address;
|
||
|
|
|
||
|
|
if (group == IX_QMGR_QUELOW_GROUP)
|
||
|
|
{
|
||
|
|
address = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QINTREG0_OFFSET);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
address = (UINT32*)(aqmBaseAddress +
|
||
|
|
IX_QMGR_QINTREG1_OFFSET);
|
||
|
|
}
|
||
|
|
|
||
|
|
ixQMgrAqmIfWordWrite (address, reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Read the status of a queue in the range 0-31.
|
||
|
|
*
|
||
|
|
* This function is used by other QMgr components to read the
|
||
|
|
* status of the queue specified by qId.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
|
||
|
|
IxQMgrQStatus *status)
|
||
|
|
{
|
||
|
|
/* Read the general status bits */
|
||
|
|
*status = ixQMgrAqmIfQRegisterBitsRead (qId,
|
||
|
|
IX_QMGR_QUELOWSTAT0_OFFSET,
|
||
|
|
IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This function will read the status of the queue specified
|
||
|
|
* by qId.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
|
||
|
|
IxQMgrQStatus *status)
|
||
|
|
{
|
||
|
|
/* Reset the status bits */
|
||
|
|
*status = 0;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Check if the queue is nearly empty,
|
||
|
|
* N.b. QUPP stat register contains status for regs 32-63 at each
|
||
|
|
* bit position so subtract 32 to get bit offset
|
||
|
|
*/
|
||
|
|
if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
|
||
|
|
IX_QMGR_QUEUPPSTAT0_OFFSET,
|
||
|
|
IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
|
||
|
|
0/*relativeBitOffset*/,
|
||
|
|
FALSE/*!reset*/))
|
||
|
|
{
|
||
|
|
*status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Check if the queue is full,
|
||
|
|
* N.b. QUPP stat register contains status for regs 32-63 at each
|
||
|
|
* bit position so subtract 32 to get bit offset
|
||
|
|
*/
|
||
|
|
if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
|
||
|
|
IX_QMGR_QUEUPPSTAT1_OFFSET,
|
||
|
|
IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
|
||
|
|
0/*relativeBitOffset*/,
|
||
|
|
FALSE/*!reset*/))
|
||
|
|
{
|
||
|
|
*status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This function is used by other QMgr components to read the
|
||
|
|
* status of the queue specified by qId.
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE void
|
||
|
|
ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
|
||
|
|
IxQMgrQStatus *qStatus)
|
||
|
|
{
|
||
|
|
if (qId < IX_QMGR_MIN_QUEUPP_QID)
|
||
|
|
{
|
||
|
|
ixQMgrAqmIfQueLowStatRead (qId, qStatus);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ixQMgrAqmIfQueUppStatRead (qId, qStatus);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This function performs a mod division
|
||
|
|
*/
|
||
|
|
IX_QMGR_AQMIF_INLINE unsigned
|
||
|
|
ixQMgrAqmIfPow2NumDivide (unsigned numerator,
|
||
|
|
unsigned denominator)
|
||
|
|
{
|
||
|
|
/* Number is evenly divisable by 2 */
|
||
|
|
return (numerator >> ixQMgrAqmIfLog2 (denominator));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restore IX_COMPONENT_NAME */
|
||
|
|
#undef IX_COMPONENT_NAME
|
||
|
|
#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
|
||
|
|
|
||
|
|
#endif/*IXQMGRAQMIF_P_H*/
|