upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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97 lines
2.8 KiB
97 lines
2.8 KiB
19 years ago
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/**
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* @file IxQMgrQAccess_p.h
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*
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* @author Intel Corporation
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* @date 30-Oct-2001
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*
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* @brief QAccess private header file
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IXQMGRQACCESS_P_H
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#define IXQMGRQACCESS_P_H
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/*
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* User defined header files
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*/
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#include "IxQMgr.h"
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/*
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* Global variables declarations.
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*/
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extern volatile UINT32 * ixQMgrAqmIfQueAccRegAddr[];
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/*
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* Initialise the Queue Access component
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*/
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void
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ixQMgrQAccessInit (void);
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/*
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* read the remainder of a multi-word queue entry
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* (the first word is already read)
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*/
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IX_STATUS
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ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
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UINT32 *entry);
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/*
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* Fast access : pop a q entry from a single word queue
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*/
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extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId);
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extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId)
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{
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return *(ixQMgrAqmIfQueAccRegAddr[qId]);
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}
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/*
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* Fast access : push a q entry in a single word queue
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*/
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extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry);
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extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry)
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{
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*(ixQMgrAqmIfQueAccRegAddr[qId]) = entry;
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}
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#endif/*IXQMGRQACCESS_P_H*/
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