upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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87 lines
2.0 KiB
87 lines
2.0 KiB
16 years ago
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/hardware.h>
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void icache_enable (void)
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{
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s32 i;
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/* disable all cache bits */
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CLR_REG( REG_SYSCFG, 0x3F);
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/* 8KB cache, write enable */
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SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
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/* clear TAG RAM bits */
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for ( i = 0; i < 256; i++)
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PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
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/* clear SET0 RAM */
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for(i=0; i < 1024; i++)
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PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
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/* clear SET1 RAM */
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for(i=0; i < 1024; i++)
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PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
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/* enable cache */
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SET_REG( REG_SYSCFG, CACHE_ENABLE);
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}
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void icache_disable (void)
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{
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/* disable all cache bits */
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CLR_REG( REG_SYSCFG, 0x3F);
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}
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int icache_status (void)
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{
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return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
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}
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void dcache_enable (void)
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{
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/* we don't have seperate instruction/data caches */
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icache_enable();
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}
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void dcache_disable (void)
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{
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/* we don't have seperate instruction/data caches */
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icache_disable();
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}
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int dcache_status (void)
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{
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/* we don't have seperate instruction/data caches */
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return icache_status();
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}
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