upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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122 lines
2.7 KiB
122 lines
2.7 KiB
11 years ago
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/*
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* (C) Copyright 2011
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* Matthias Weisser <weisserm@arcor.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* imx25lcdc.c - Graphic interface for i.MX25 lcd controller
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <video_fb.h>
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#include "videomodes.h"
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/*
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* 4MB (at the end of system RAM)
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*/
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#define VIDEO_MEM_SIZE 0x400000
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#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
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/*
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* Graphic Device
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*/
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static GraphicDevice imx25fb;
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void *video_hw_init(void)
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{
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struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE;
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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GraphicDevice *pGD = &imx25fb;
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char *s;
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u32 *videomem;
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memset(pGD, 0, sizeof(GraphicDevice));
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pGD->gdfIndex = GDF_16BIT_565RGB;
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pGD->gdfBytesPP = 2;
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pGD->memSize = VIDEO_MEM_SIZE;
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pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
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videomem = (u32 *)pGD->frameAdrs;
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s = getenv("videomode");
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if (s != NULL) {
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struct ctfb_res_modes var_mode;
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u32 lsr, lpcr, lhcr, lvcr;
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unsigned long div;
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int bpp;
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/* Disable all clocks of the LCDC */
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writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0);
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writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1);
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bpp = video_get_params(&var_mode, s);
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if (bpp == 0) {
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var_mode.xres = 320;
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var_mode.yres = 240;
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var_mode.pixclock = 154000;
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var_mode.left_margin = 68;
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var_mode.right_margin = 20;
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var_mode.upper_margin = 4;
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var_mode.lower_margin = 18;
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var_mode.hsync_len = 40;
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var_mode.vsync_len = 6;
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var_mode.sync = 0;
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var_mode.vmode = 0;
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}
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/* Fill memory with white */
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memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
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imx25fb.winSizeX = var_mode.xres;
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imx25fb.winSizeY = var_mode.yres;
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/* LCD base clock is 66.6MHZ. We do calculations in kHz */
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div = 66000 / (1000000000L / var_mode.pixclock);
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if (div > 63)
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div = 63;
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if (0 == div)
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div = 1;
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lsr = ((var_mode.xres / 16) << 20) |
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var_mode.yres;
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lpcr = (1 << 31) |
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(1 << 30) |
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(5 << 25) |
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(1 << 23) |
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(1 << 22) |
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(1 << 19) |
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(1 << 7) |
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div;
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lhcr = (var_mode.right_margin << 0) |
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(var_mode.left_margin << 8) |
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(var_mode.hsync_len << 26);
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lvcr = (var_mode.lower_margin << 0) |
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(var_mode.upper_margin << 8) |
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(var_mode.vsync_len << 26);
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writel((uint32_t)videomem, &lcdc->lssar);
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writel(lsr, &lcdc->lsr);
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writel(var_mode.xres * 2 / 4, &lcdc->lvpwr);
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writel(lpcr, &lcdc->lpcr);
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writel(lhcr, &lcdc->lhcr);
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writel(lvcr, &lcdc->lvcr);
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writel(0x00040060, &lcdc->ldcr);
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writel(0xA90300, &lcdc->lpccr);
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/* Ensable all clocks of the LCDC */
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writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0);
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writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1);
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}
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return pGD;
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}
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