upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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238 lines
7.9 KiB
238 lines
7.9 KiB
17 years ago
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/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <commproc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <watchdog.h>
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#ifdef CONFIG_SERIAL_MULTI
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#include <serial.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_IOP480
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#define SPU_BASE 0x40000000
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#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
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#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
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#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
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#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
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#define spu_BRateDivh 0x10 /* Baud rate divisor high */
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#define spu_BRateDivl 0x14 /* Baud rate divisor low */
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#define spu_CtlReg 0x18 /* Control Register */
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#define spu_RxCmd 0x1c /* Rx Command Register */
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#define spu_TxCmd 0x20 /* Tx Command Register */
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#define spu_RxBuff 0x24 /* Rx data buffer */
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#define spu_TxBuff 0x24 /* Tx data buffer */
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/*-----------------------------------------------------------------------------+
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| Line Status Register.
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+-----------------------------------------------------------------------------*/
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#define asyncLSRport1 0x40000000
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#define asyncLSRport1set 0x40000004
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#define asyncLSRDataReady 0x80
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#define asyncLSRFramingError 0x40
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#define asyncLSROverrunError 0x20
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#define asyncLSRParityError 0x10
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#define asyncLSRBreakInterrupt 0x08
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#define asyncLSRTxHoldEmpty 0x04
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#define asyncLSRTxShiftEmpty 0x02
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/*-----------------------------------------------------------------------------+
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| Handshake Status Register.
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+-----------------------------------------------------------------------------*/
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#define asyncHSRport1 0x40000008
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#define asyncHSRport1set 0x4000000c
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#define asyncHSRDsr 0x80
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#define asyncLSRCts 0x40
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/*-----------------------------------------------------------------------------+
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| Control Register.
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+-----------------------------------------------------------------------------*/
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#define asyncCRport1 0x40000018
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#define asyncCRNormal 0x00
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#define asyncCRLoopback 0x40
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#define asyncCRAutoEcho 0x80
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#define asyncCRDtr 0x20
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#define asyncCRRts 0x10
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#define asyncCRWordLength7 0x00
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#define asyncCRWordLength8 0x08
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#define asyncCRParityDisable 0x00
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#define asyncCRParityEnable 0x04
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#define asyncCREvenParity 0x00
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#define asyncCROddParity 0x02
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#define asyncCRStopBitsOne 0x00
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#define asyncCRStopBitsTwo 0x01
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#define asyncCRDisableDtrRts 0x00
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/*-----------------------------------------------------------------------------+
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| Receiver Command Register.
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+-----------------------------------------------------------------------------*/
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#define asyncRCRport1 0x4000001c
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#define asyncRCRDisable 0x00
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#define asyncRCREnable 0x80
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#define asyncRCRIntDisable 0x00
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#define asyncRCRIntEnabled 0x20
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#define asyncRCRDMACh2 0x40
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#define asyncRCRDMACh3 0x60
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#define asyncRCRErrorInt 0x10
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#define asyncRCRPauseEnable 0x08
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/*-----------------------------------------------------------------------------+
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| Transmitter Command Register.
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+-----------------------------------------------------------------------------*/
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#define asyncTCRport1 0x40000020
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#define asyncTCRDisable 0x00
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#define asyncTCREnable 0x80
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#define asyncTCRIntDisable 0x00
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#define asyncTCRIntEnabled 0x20
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#define asyncTCRDMACh2 0x40
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#define asyncTCRDMACh3 0x60
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#define asyncTCRTxEmpty 0x10
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#define asyncTCRErrorInt 0x08
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#define asyncTCRStopPause 0x04
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#define asyncTCRBreakGen 0x02
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/*-----------------------------------------------------------------------------+
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| Miscellanies defines.
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+-----------------------------------------------------------------------------*/
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#define asyncTxBufferport1 0x40000024
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#define asyncRxBufferport1 0x40000024
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#define asyncDLABLsbport1 0x40000014
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#define asyncDLABMsbport1 0x40000010
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#define asyncXOFFchar 0x13
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#define asyncXONchar 0x11
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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int serial_init (void)
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{
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volatile char val;
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unsigned short br_reg;
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br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
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/*
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* Init onboard UART
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*/
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out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
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out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
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out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
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out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
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out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
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out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
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out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
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val = in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
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return (0);
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}
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void serial_setbrg (void)
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{
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unsigned short br_reg;
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br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
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out_8((u8 *)SPU_BASE + spu_BRateDivl,
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(br_reg & 0x00ff)); /* Set baud rate divisor... */
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out_8((u8 *)SPU_BASE + spu_BRateDivh,
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((br_reg & 0xff00) >> 8)); /* ... */
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}
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void serial_putc (const char c)
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{
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if (c == '\n')
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serial_putc ('\r');
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/* load status from handshake register */
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if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
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out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
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out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */
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while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) {
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if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
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out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
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}
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}
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void serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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int serial_getc ()
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{
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unsigned char status = 0;
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while (1) {
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status = in_8((u8 *)asyncLSRport1);
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if ((status & asyncLSRDataReady) != 0x0) {
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break;
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}
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if ((status & ( asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt )) != 0) {
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(void) out_8((u8 *)asyncLSRport1,
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asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt );
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}
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}
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return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1));
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}
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int serial_tstc ()
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{
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unsigned char status;
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status = in_8((u8 *)asyncLSRport1);
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if ((status & asyncLSRDataReady) != 0x0) {
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return (1);
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}
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if ((status & ( asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt )) != 0) {
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(void) out_8((u8 *)asyncLSRport1,
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asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt);
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}
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return 0;
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}
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#endif /* CONFIG_IOP480 */
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