upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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291 lines
15 KiB
291 lines
15 KiB
16 years ago
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/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Copyright (C) 2006 Micronas GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _REG_EBI_PREMIUM_H_
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#define _REG_EBI_PREMIUM_H_
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#define EBI_BASE 0x00000000
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/* Relative offsets of the register adresses */
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#define EBI_CPU_IO_ACCS_OFFS 0x00000000
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#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
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#define EBI_IO_ACCS_DATA_OFFS 0x00000004
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#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
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#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
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#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
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#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
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#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
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#define EBI_CTRL_OFFS 0x00000010
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#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
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#define EBI_IRQ_MASK_OFFS 0x00000018
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#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
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#define EBI_IRQ_MASK2_OFFS 0x0000001C
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#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
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#define EBI_TAG1_SYS_ID_OFFS 0x00000030
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#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
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#define EBI_TAG2_SYS_ID_OFFS 0x00000040
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#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
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#define EBI_TAG3_SYS_ID_OFFS 0x00000050
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#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
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#define EBI_TAG4_SYS_ID_OFFS 0x00000060
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#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
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#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
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#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
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#define EBI_STATUS_OFFS 0x00000080
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#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
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#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
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#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
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#define EBI_SIG_LEVEL_OFFS 0x00000088
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#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
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#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
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#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
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#define EBI_CRC_GEN_OFFS 0x00000090
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#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
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#define EBI_EXT_ADDR_OFFS 0x000000A0
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#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
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#define EBI_IRQ_STATUS_OFFS 0x000000B0
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#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
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#define EBI_IRQ_STATUS2_OFFS 0x000000B4
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#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
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#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
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#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
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#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
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#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
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#define EBI_ECC0_OFFS 0x000000D0
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#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
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#define EBI_ECC1_OFFS 0x000000D4
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#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
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#define EBI_ECC2_OFFS 0x000000D8
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#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
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#define EBI_ECC3_OFFS 0x000000DC
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#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
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#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
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#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
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#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
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#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
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#define EBI_DEV1_CONFIG1_OFFS 0x00000108
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#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
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#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
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#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
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#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
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#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
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#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
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#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
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#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
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#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
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#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
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#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
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#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
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#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
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#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
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#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
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#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
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#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
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#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
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#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
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#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
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#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
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#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
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#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
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#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
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#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
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#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
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#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
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#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
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#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
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#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
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#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
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#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
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#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
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#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
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#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
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#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
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#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
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#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
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#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
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#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
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#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
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#define EBI_DEV2_CONFIG1_OFFS 0x00000208
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#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
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#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
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#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
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#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
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#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
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#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
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#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
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#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
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#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
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#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
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#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
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#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
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#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
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#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
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#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
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#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
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#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
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#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
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#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
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#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
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#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
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#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
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#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
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#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
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#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
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#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
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#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
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#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
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#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
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#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
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#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
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#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
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#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
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#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
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#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
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#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
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#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
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#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
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#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
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#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
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#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
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#define EBI_DEV3_CONFIG1_OFFS 0x00000308
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#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
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#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
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#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
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#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
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#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
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#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
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#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
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#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
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#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
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#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
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#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
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#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
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#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
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#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
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#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
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#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
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#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
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#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
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#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
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#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
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#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
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#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
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#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
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#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
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#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
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#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
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#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
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#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
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#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
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#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
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#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
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#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
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#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
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#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
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#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
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#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
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#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
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#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
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#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
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#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
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#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
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#define EBI_DEV4_CONFIG1_OFFS 0x00000408
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#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
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#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
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#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
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#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
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#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
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#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
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#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
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#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
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#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
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#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
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#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
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#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
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#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
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#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
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#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
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#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
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#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
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#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
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#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
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#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
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#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
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#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
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#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
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#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
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#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
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#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
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#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
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#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
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#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
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#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
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#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
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#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
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#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
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#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
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#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
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#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
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#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
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#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
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#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
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#define EBI_CNT_FL_PROGR_OFFS 0x00000904
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#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
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#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
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#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
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#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
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#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
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#define EBI_CNT_ACK_OFFS 0x00000918
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#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
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#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
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#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
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#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
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#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
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#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
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#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
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#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
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#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
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#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
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#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
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#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
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#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
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#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
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#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
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#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
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#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
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#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
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#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
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#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
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#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
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#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
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#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
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#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
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#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
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#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
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#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
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#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
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#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
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#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
|
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#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
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#endif
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