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upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
/* SPDX-License-Identifier: GPL-2.0+ */
arm: lpc32xx: gpio macro for pin mapping Add LPC32xx GPIO interface macro for pin mapping. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
9 years ago
/*
* LPC32xx GPIO interface macro for pin mapping.
*
* (C) Copyright 2015 DENX Software Engineering GmbH
* Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
*/
#ifndef _LPC32XX_GPIO_GRP_H
#define _LPC32XX_GPIO_GRP_H
/*
* Macro to map the pin for the lpc32xx_gpio driver.
gpio: lpc32xx: fix issues with port3 gpio The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
9 years ago
* Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
arm: lpc32xx: gpio macro for pin mapping Add LPC32xx GPIO interface macro for pin mapping. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
9 years ago
* mapping is done per register, as group of 32.
* (see drivers/gpio/lpc32xx_gpio.c for details).
* - macros can be use with the following pins:
* P0.0 - P0.7
* P1.0 - P1.23
* P2.0 - P2.12
* P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
* P3 GPO_0 - GPO_23
* P3 GPIO_0 - GPIO_5 (output register only)
*/
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP 32
#define LPC32XX_GPIO_P2_GRP 64
#define LPC32XX_GPO_P3_GRP 96
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
gpio: lpc32xx: fix issues with port3 gpio The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
9 years ago
#define LPC32XX_GPI_P3_GRP 128
arm: lpc32xx: gpio macro for pin mapping Add LPC32xx GPIO interface macro for pin mapping. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
9 years ago
/*
* A specific GPIO can be selected with this macro
* ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
* See the LPC32x0 User's guide for GPIO group numbers
*/
#define LPC32XX_GPIO(x, y) ((x) + (y))
#endif /* _LPC32XX_GPIO_GRP_H */