upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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58 lines
1.5 KiB
58 lines
1.5 KiB
7 years ago
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Actions Semi S900 Clock Definitions
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*
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* Copyright (C) 2015 Actions Semi Co., Ltd.
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* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*
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*/
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#ifndef _OWL_CLK_S900_H_
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#define _OWL_CLK_S900_H_
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#include <clk-uclass.h>
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struct owl_clk_priv {
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phys_addr_t base;
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};
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/* BUSCLK register definitions */
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#define CMU_PDBGDIV_8 7
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#define CMU_PDBGDIV_SHIFT 26
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#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
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#define CMU_PERDIV_8 7
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#define CMU_PERDIV_SHIFT 20
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#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
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#define CMU_NOCDIV_2 1
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#define CMU_NOCDIV_SHIFT 19
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#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
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#define CMU_DMMCLK_SRC_APLL 2
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#define CMU_DMMCLK_SRC_SHIFT 10
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#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
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#define CMU_APBCLK_DIV BIT(8)
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#define CMU_NOCCLK_SRC BIT(7)
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#define CMU_AHBCLK_DIV BIT(4)
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#define CMU_CORECLK_MASK 3
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#define CMU_CORECLK_CPLL BIT(1)
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#define CMU_CORECLK_HOSC BIT(0)
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/* COREPLL register definitions */
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#define CMU_COREPLL_EN BIT(9)
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#define CMU_COREPLL_HOSC_EN BIT(8)
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#define CMU_COREPLL_OUT (1104 / 24)
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/* DEVPLL register definitions */
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#define CMU_DEVPLL_CLK BIT(12)
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#define CMU_DEVPLL_EN BIT(8)
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#define CMU_DEVPLL_OUT (660 / 6)
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/* UARTCLK register definitions */
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#define CMU_UARTCLK_SRC_DEVPLL BIT(16)
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/* DEVCLKEN1 register definitions */
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#define CMU_DEVCLKEN1_UART5 BIT(21)
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#define PLL_STABILITY_WAIT_US 50
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#endif
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