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upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/arch/arm/include/asm/arch-rockchip/pwm.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
/* SPDX-License-Identifier: GPL-2.0+ */
pwm: rockchip: Add a PWM driver for Rockchip SoCs Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
9 years ago
/*
* (C) Copyright 2016 Google, Inc
* (C) Copyright 2008-2014 Rockchip Electronics
*/
#ifndef _ASM_ARCH_PWM_H
#define _ASM_ARCH_PWM_H
struct rk3288_pwm {
u32 cnt;
rockchip: rkpwm: fix the register sequence Reference to kernel source code, rockchip pwm has three type, we are using v2 for rk3288 and rk3399, so let's update the register to sync with pwm_data_v2 in kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
8 years ago
u32 period_hpr;
rockchip: pwm: fix the register layout for the PWM controller According to rk3288 spec, the pwm register order is: PWM_PWM0_CNT, PWM_PWM0_PERIOD_HPR, PWM_PWM0_DUTY_LPR, PWM_PWM0_CTRL but the source code's order is: struct rk3288_pwm { u32 cnt; u32 duty_lpr; u32 period_hpr; u32 ctrl; }; So, correct it here. It is the same as RK3399. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Edited the commit message: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
8 years ago
u32 duty_lpr;
pwm: rockchip: Add a PWM driver for Rockchip SoCs Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
9 years ago
u32 ctrl;
};
check_member(rk3288_pwm, ctrl, 0xc);
#define RK_PWM_DISABLE (0 << 0)
#define RK_PWM_ENABLE (1 << 0)
#define PWM_ONE_SHOT (0 << 1)
#define PWM_CONTINUOUS (1 << 1)
#define RK_PWM_CAPTURE (1 << 2)
#define PWM_DUTY_POSTIVE (1 << 3)
#define PWM_DUTY_NEGATIVE (0 << 3)
rockchip: pwm: add mask for config setting Use mask to clear old setting before direct set the new config, or else there it will mess up the config when it's not the same with default value. Fixes: 3851059 rockchip: Setup default PWM flags Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years ago
#define PWM_DUTY_MASK (1 << 3)
pwm: rockchip: Add a PWM driver for Rockchip SoCs Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
9 years ago
#define PWM_INACTIVE_POSTIVE (1 << 4)
#define PWM_INACTIVE_NEGATIVE (0 << 4)
rockchip: pwm: add mask for config setting Use mask to clear old setting before direct set the new config, or else there it will mess up the config when it's not the same with default value. Fixes: 3851059 rockchip: Setup default PWM flags Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years ago
#define PWM_INACTIVE_MASK (1 << 4)
pwm: rockchip: Add a PWM driver for Rockchip SoCs Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
9 years ago
#define PWM_OUTPUT_LEFT (0 << 5)
#define PWM_OUTPUT_CENTER (1 << 5)
#define PWM_LP_ENABLE (1 << 8)
#define PWM_LP_DISABLE (0 << 8)
#define PWM_SEL_SCALE_CLK (1 << 9)
#define PWM_SEL_SRC_CLK (0 << 9)
#endif