u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
 */

#ifndef _TEGRA114_SYSCTR_H_
#define _TEGRA114_SYSCTR_H_

struct sysctr_ctlr {
	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
	u32 reserved1[4];	/* 0x10 - 0x1C */
	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
	u32 reserved2[1002];	/* 0x28 - 0xFCC */
	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
};

#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */

#endif	/* _TEGRA114_SYSCTR_H_ */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 7 years ago			`/* SPDX-License-Identifier: GPL-2.0 */`
Tegra114: Initialize System Counter (TSC) with osc frequency T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> 12 years ago			`/*`
			`* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.`
			`*/`

			`#ifndef _TEGRA114_SYSCTR_H_`
			`#define _TEGRA114_SYSCTR_H_`

			`struct sysctr_ctlr {`
			`u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */`
			`u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */`
			`u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */`
			`u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */`
			`u32 reserved1[4]; /* 0x10 - 0x1C */`
			`u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */`
			`u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */`
			`u32 reserved2[1002]; /* 0x28 - 0xFCC */`
			`u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */`
			`};`

			`#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */`
			`#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */`

			`#endif /* _TEGRA114_SYSCTR_H_ */`