u-boot/arch/arm/mach-bcm283x/phys2bus.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Stephen Warren
 */

#include <config.h>
#include <phys2bus.h>

unsigned long phys_to_bus(unsigned long phys)
{
#ifndef CONFIG_BCM2835
	return 0xc0000000 | phys;
#else
	return 0x40000000 | phys;
#endif
}

unsigned long bus_to_phys(unsigned long bus)
{
	return bus & ~0xc0000000;
}
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 6 years ago			`// SPDX-License-Identifier: GPL-2.0+`
ARM: bcm2835: implement phys_to_bus/bus_to_phys The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally access DRAM via this same L2 cache (although they always bypass the L1 cache). Peripherals select whether to use or bypass the cache via the top two bits of the bus address. An IOMMU exists between the ARM CPU and the rest of the system. This controls whether the ARM CPU's accesses use or bypass the L1 and/or L2 cache. This IOMMU is configured/controlled exclusively by the VideoCore CPU. In order for DRAM accesses made by the ARM core to be coherent with accesses made by other DMA peripherals, we must program a bus address into those peripherals that causes the peripheral's accesses to use the same set of caches that the ARM core's accesses will use. On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of the L2 cache. This corresponds to addresses based at 0x40000000. On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of the L2 cache. This corresponds to addresses based at 0xc0000000. This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according to those rules. For full details of this setup, please see Dom Cobley's description at: http://lists.denx.de/pipermail/u-boot/2015-March/208201.html http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038 https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> 9 years ago			`/*`
			`* Copyright 2015 Stephen Warren`
			`*/`

			`#include <config.h>`
			`#include <phys2bus.h>`

			`unsigned long phys_to_bus(unsigned long phys)`
			`{`
ARM: bcm283x: don't always define CONFIG_BCM2835 Currently, CONFIG_BCM2835 is defined for all BCM283x builds and _BCM2836 is defined when building for that SoC. That means there isn't a single define that means "exactly BCM2835". This will complicate future patches where BCM2835-vs-anything-else needs to be determined simply. Modify the code to define one or the other of CONFIG_BCM2835/BCM2836 so future patches are simpler. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com> 8 years ago			`#ifndef CONFIG_BCM2835`
ARM: bcm2835: implement phys_to_bus/bus_to_phys The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally access DRAM via this same L2 cache (although they always bypass the L1 cache). Peripherals select whether to use or bypass the cache via the top two bits of the bus address. An IOMMU exists between the ARM CPU and the rest of the system. This controls whether the ARM CPU's accesses use or bypass the L1 and/or L2 cache. This IOMMU is configured/controlled exclusively by the VideoCore CPU. In order for DRAM accesses made by the ARM core to be coherent with accesses made by other DMA peripherals, we must program a bus address into those peripherals that causes the peripheral's accesses to use the same set of caches that the ARM core's accesses will use. On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of the L2 cache. This corresponds to addresses based at 0x40000000. On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of the L2 cache. This corresponds to addresses based at 0xc0000000. This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according to those rules. For full details of this setup, please see Dom Cobley's description at: http://lists.denx.de/pipermail/u-boot/2015-March/208201.html http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038 https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> 9 years ago			`return 0xc0000000 \| phys;`
			`#else`
			`return 0x40000000 \| phys;`
			`#endif`
			`}`

			`unsigned long bus_to_phys(unsigned long bus)`
			`{`
			`return bus & ~0xc0000000;`
			`}`