Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
53086 Commits
3 Branches
0 Tags
148 MiB
Tag: Branch: Tree: b85f4fe70c
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'b85f4fe70c'
${ noResults }
u-boot/configs/T1042RDB_PI_NAND_SECURE_BOO...

74 lines
1.8 KiB
Raw Normal View History Unescape

powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_PPC=y
configs: Migrate CONFIG_SYS_TEXT_BASE On the NIOS2 and Xtensa architectures, we do not have CONFIG_SYS_TEXT_BASE set. This is a strict migration of the current values into the defconfig and removing them from the headers. I did not attempt to add more default values in and for now will leave that to maintainers. Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
CONFIG_SYS_TEXT_BASE=0x30001000
Convert CONFIG_SPL_LIBCOMMON_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_LIBCOMMON_SUPPORT=y
Convert CONFIG_SPL_LIBGENERIC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_LIBGENERIC_SUPPORT=y
Sync defconfig files by savedefconfig Generated by "tools/moveconfig -s". This will make config moves easier. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years ago
CONFIG_SECURE_BOOT=y
Convert CONFIG_SPL_SERIAL_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_SERIAL_SUPPORT=y
configs: Re-sync Signed-off-by: Tom Rini <trini@konsulko.com>
8 years ago
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
CONFIG_SPL=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_MPC85xx=y
powerpc: T1042RDB_PI: Split from T1042RDB in Kconfig Use separated TARGET_T1042RDB_PI to simplify config options. Remove macro CONFIG_T1042RDB_PI. Signed-off-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_TARGET_T1042RDB_PI=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
Convert CONFIG_NAND to Kconfig This converts the following to Kconfig: CONFIG_NAND Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Sync up a few more, add imply's] Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_BOOTDELAY=0
Convert SILENT_CONSOLE options to Kconfig Move these option to Kconfig and tidy up existing uses. The Power PC boards don't have a suitable common element: the common header files don't appear to line up with the Kconfig files as far as I can tell. This results in a lot of defconfig changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> [trini: Re-migrate, update common/console.c logic] Signed-off-by: Tom Rini <trini@konsulko.com>
8 years ago
CONFIG_SILENT_CONSOLE=y
Convert CONFIG_SYS_CONSOLE_IS_IN_ENV and CONFIG_CONSOLE_MUX to Kconfig This converts the following to Kconfig: CONFIG_SYS_CONSOLE_IS_IN_ENV CONFIG_CONSOLE_MUX Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Re-order, re-migrate] Signed-off-by: Tom Rini <trini@konsulko.com>
8 years ago
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Convert CONFIG_BOARD_EARLY_INIT_F to Kconfig This converts the following to Kconfig: CONFIG_BOARD_EARLY_INIT_F Signed-off-by: Simon Glass <sjg@chromium.org>
7 years ago
CONFIG_BOARD_EARLY_INIT_F=y
treewide: Migrate CONFIG_BOARD_EARLY_INIT_R to Kconfig Migrate the CONFIG_BOARD_EARLY_INIT_R option to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years ago
CONFIG_BOARD_EARLY_INIT_R=y
configs: Migrate CONFIG_SPL_FRAMEWORK Migrate the option CONFIG_SPL_FRAMEWORK and make this gate most of the current set of options we have in Kconfig. We will need to have some options available for SPL and !SPL_FRAMEWORK so this is important. In a few cases we re-order existing options so that we have less escapes from the SPL_FRAMEWORK guard. Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
# CONFIG_SPL_FRAMEWORK is not set
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_CRYPTO_SUPPORT=y
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_HASH_SUPPORT=y
configs: Re-sync Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
Convert CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
CONFIG_SPL_NAND_SUPPORT=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_HUSH_PARSER=y
cmd: Toggle the default value of CONFIG_CMD_IMLS Having this as a 'default y' is rather annoying because it doesn't actually compile unless other options are defined in the board header: ../cmd/bootm.c: In function 'do_imls_nor': ../cmd/bootm.c:330:7: error: 'CONFIG_SYS_MAX_FLASH_BANKS' undeclared (first use in this function); did you mean 'CONFIG_SYS_MAX_FLASH_SECT'? i < CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) { Make it 'default n' so people who develop new boards that start from a blank defconfig have one less compilation failure to debug. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
7 years ago
CONFIG_CMD_IMLS=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_CMD_GREPENV=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_CMD_I2C=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
Convert CONFIG_CMD_BMP to Kconfig This converts the following to Kconfig: CONFIG_CMD_BMP Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add depends on LCD || DM_VIDEO || VIDEO] Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_CMD_BMP=y
cmd: add Kconfig option for 'date' command Signed-off-by: Chris Packham <judge.packham@gmail.com> [trini: default y if DM_RTC, re-sync] Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_CMD_DATE=y
cmd: Kconfig: Move CONFIG_MP to Kconfig This patch moves CONFIG_MP to Kconfig Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years ago
CONFIG_MP=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
Kconfig: Migrate MTDIDS_DEFAULT / MTDPARTS_DEFAULT We move all instances of CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT from the header files to the defconfig files. There's a few cases here where we need to expand upon what was in the header file. Tested-by: Adam Ford <aford173@gmail.com> #omap3_logic Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
configs: Resync with savedefconfig Signed-off-by: Tom Rini <trini@konsulko.com>
8 years ago
CONFIG_DM=y
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_DM=y
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_SYS_FSL_DDR3=y
treewide: Migrate CONFIG_FSL_ESDHC to Kconfig Migrate the CONFIG_FSL_ESDHC option to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years ago
CONFIG_FSL_ESDHC=y
Convert CONFIG_MTD_PARTITIONS et al to Kconfig This converts the following to Kconfig: CONFIG_MTD_PARTITIONS CONFIG_MTD_DEVICE Signed-off-by: Adam Ford <aford173@gmail.com>
6 years ago
CONFIG_MTD_PARTITIONS=y
Convert CONFIG_FLASH_CFI_DRIVER et al to Kconfig This converts the following to Kconfig: CONFIG_FLASH_CFI_DRIVER CONFIG_SYS_FLASH_USE_BUFFER_WRITE CONFIG_FLASH_CFI_MTD CONFIG_SYS_FLASH_PROTECTION CONFIG_SYS_FLASH_CFI Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Re-migrate] Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
Convert CONFIG_NAND to Kconfig This converts the following to Kconfig: CONFIG_NAND Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Sync up a few more, add imply's] Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_NAND=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
Move PHYLIB to Kconfig Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years ago
CONFIG_PHYLIB=y
configs: Finish migration of PHY_GIGE Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_PHY_GIGE=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_E1000=y
Convert CONFIG_MII et al to Kconfig This converts the following to Kconfig: CONFIG_MII CONFIG_DRIVER_TI_EMAC Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
6 years ago
CONFIG_MII=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_SYS_NS16550=y
Convert CONFIG_SPI to Kconfig This converts the following to Kconfig: CONFIG_SPI This partly involves updating code that assumes that CONFIG_SPI implies things that are specific to the MPC8xx SPI driver. For now, just update the CONFIG tests. This also involves reworking the default for CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a reasonable default, as it does not cause any compile failures. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
CONFIG_SPI=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_FSL_ESPI=y
configs: Migrate CONFIG_USB_STORAGE In some cases we were missing CONFIG_USB=y so enable that when needed. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
8 years ago
CONFIG_USB=y
CONFIG_USB_STORAGE=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_VIDEO=y
Convert CONFIG_CFB_CONSOLE_ANSI to Kconfig This converts the following to Kconfig: CONFIG_CFB_CONSOLE_ANSI Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
8 years ago
CONFIG_CFB_CONSOLE_ANSI=y
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
8 years ago
CONFIG_RSA=y
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
8 years ago
CONFIG_SPL_RSA=y
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_RSA_SOFTWARE_EXP=y
configs: Resync with savedefconfig Signed-off-by: Tom Rini <trini@konsulko.com>
8 years ago
CONFIG_OF_LIBFDT=y