upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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221 lines
12 KiB
221 lines
12 KiB
17 years ago
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/*
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* Ethernet MAC Masks
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*/
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#ifndef __BFIN_PERIPHERAL_EMAC__
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#define __BFIN_PERIPHERAL_EMAC__
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/* EMAC_OPMODE Masks */
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#define RE 0x00000001 /* Receiver Enable */
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#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
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#define HU 0x00000010 /* Hash Filter Unicast Address */
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#define HM 0x00000020 /* Hash Filter Multicast Address */
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#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
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#define PR 0x00000080 /* Promiscuous Mode Enable */
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#define IFE 0x00000100 /* Inverse Filtering Enable */
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#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
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#define PBF 0x00000400 /* Pass Bad Frames Enable */
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#define PSF 0x00000800 /* Pass Short Frames Enable */
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#define RAF 0x00001000 /* Receive-All Mode */
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#define TE 0x00010000 /* Transmitter Enable */
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#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
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#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
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#define DC 0x00080000 /* Deferral Check */
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#define BOLMT 0x00300000 /* Back-Off Limit */
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#define BOLMT_10 0x00000000 /* 10-bit range */
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#define BOLMT_8 0x00100000 /* 8-bit range */
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#define BOLMT_4 0x00200000 /* 4-bit range */
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#define BOLMT_1 0x00300000 /* 1-bit range */
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#define DRTY 0x00400000 /* Disable TX Retry On Collision */
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#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
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#define RMII 0x01000000 /* RMII/MII* Mode */
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#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
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#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
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#define LB 0x08000000 /* Internal Loopback Enable */
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#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
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/* EMAC_STAADD Masks */
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#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
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#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
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#define STADISPRE 0x00000004 /* Disable Preamble Generation */
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#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
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#define REGAD 0x000007C0 /* STA Register Address */
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#define PHYAD 0x0000F800 /* PHY Device Address */
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#define SET_REGAD(x) (((x) & 0x1F) << 6) /* Set STA Register Address */
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#define SET_PHYAD(x) (((x) & 0x1F) << 11) /* Set PHY Device Address */
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/* EMAC_STADAT Mask */
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#define STADATA 0x0000FFFF /* Station Management Data */
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/* EMAC_FLC Masks */
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#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
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#define FLCE 0x00000002 /* Flow Control Enable */
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#define PCF 0x00000004 /* Pass Control Frames */
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#define BKPRSEN 0x00000008 /* Enable Backpressure */
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#define FLCPAUSE 0xFFFF0000 /* Pause Time */
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#define SET_FLCPAUSE(x) (((x) & 0xFFFF) << 16) /* Set Pause Time */
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/* EMAC_WKUP_CTL Masks */
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#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
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#define MPKE 0x00000002 /* Magic Packet Enable */
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#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
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#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
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#define MPKS 0x00000020 /* Magic Packet Received Status */
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#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
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/* EMAC_WKUP_FFCMD Masks */
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#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
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#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
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#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
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#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
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#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
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#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
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#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
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#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
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/* EMAC_WKUP_FFOFF Masks */
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#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
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#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
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#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
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#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
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#define SET_WF0_OFF(x) (((x) & 0xFF) << 0) /* Set Wake-Up Filter 0 Byte Offset */
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#define SET_WF1_OFF(x) (((x) & 0xFF) << 8) /* Set Wake-Up Filter 1 Byte Offset */
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#define SET_WF2_OFF(x) (((x) & 0xFF) << 16) /* Set Wake-Up Filter 2 Byte Offset */
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#define SET_WF3_OFF(x) (((x) & 0xFF) << 24) /* Set Wake-Up Filter 3 Byte Offset */
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/* Set ALL Offsets */
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#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
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/* EMAC_WKUP_FFCRC0 Masks */
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#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
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#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
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#define SET_WF0_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 0 Target CRC */
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#define SET_WF1_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 1 Target CRC */
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/* EMAC_WKUP_FFCRC1 Masks */
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#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
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#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
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#define SET_WF2_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 2 Target CRC */
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#define SET_WF3_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 3 Target CRC */
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/* EMAC_SYSCTL Masks */
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#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
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#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
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#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
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#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
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#define SET_MDCDIV(x) (((x) & 0x3F) << 8) /* Set MDC Clock Divisor */
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/* EMAC_SYSTAT Masks */
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#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
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#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
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#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
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#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
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#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
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#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
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#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
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#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
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/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
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#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
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#define RX_COMP 0x00001000 /* RX Frame Complete */
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#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
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#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
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#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
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#define RX_CRC 0x00010000 /* RX Frame CRC Error */
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#define RX_LEN 0x00020000 /* RX Frame Length Error */
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#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
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#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
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#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
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#define RX_PHY 0x00200000 /* RX Frame PHY Error */
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#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
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#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
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#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
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#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
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#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
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#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
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#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
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#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
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#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
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#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
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/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
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#define TX_COMP 0x00000001 /* TX Frame Complete */
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#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
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#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
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#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
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#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
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#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
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#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
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#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
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#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
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#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
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#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
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#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
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#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
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#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
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#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
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/* EMAC_MMC_CTL Masks */
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#define RSTC 0x00000001 /* Reset All Counters */
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#define CROLL 0x00000002 /* Counter Roll-Over Enable */
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#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
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#define MMCE 0x00000008 /* Enable MMC Counter Operation */
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/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
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#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
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#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
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#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
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#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
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#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
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#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
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#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
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#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
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#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
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#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
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#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
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#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
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#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
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#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
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#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
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#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
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#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
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#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
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#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
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#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
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#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
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#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
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#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
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#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
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/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
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#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
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#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
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#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
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#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
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#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
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#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
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#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
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#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
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#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
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#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
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#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
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#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
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#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
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#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
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#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
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#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
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#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
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#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
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#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
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#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
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#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
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#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
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#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
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#endif
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