upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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279 lines
11 KiB
279 lines
11 KiB
20 years ago
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/*
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* Configuation settings for the esd TASREG board.
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*
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* (C) Copyright 2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _TASREG_H
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#define _TASREG_H
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#ifndef __ASSEMBLY__
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#include <asm/m5249.h>
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#endif
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCF52x2 /* define processor family */
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#define CONFIG_M5249 /* define processor type */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#define CONFIG_BAUDRATE 19200
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#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#undef CONFIG_WATCHDOG
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#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
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CFG_CMD_BSP | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C ) & \
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~(CFG_CMD_NET))
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CFG_PROMPT "=> "
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#define CFG_LONGHELP /* undef to save memory */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CFG_LOAD_ADDR 0x200000 /* default load address */
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#define CFG_MEMTEST_START 0x400
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#define CFG_MEMTEST_END 0x380000
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#define CFG_HZ 1000
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/*
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* Clock configuration: enable only one of the following options
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*/
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#if 0 /* this setting will run the cpu at 11MHz */
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#define CFG_PLL_BYPASS 1 /* bypass PLL for test purpose */
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#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */
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#define CFG_CLK 11289600 /* PLL bypass */
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#endif
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#if 0 /* this setting will run the cpu at 70MHz */
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#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
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#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */
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#define CFG_CLK 72185018 /* The next lower speed */
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#endif
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#if 1 /* this setting will run the cpu at 140MHz */
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#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
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#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */
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#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */
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#endif
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CFG_MBAR 0x10000000 /* Register Base Addrs */
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#define CFG_MBAR2 0x80000000
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/*-----------------------------------------------------------------------
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* I2C
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*/
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#define CONFIG_SOFT_I2C
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
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/* 32 byte page write mode using*/
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/* last 5 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#if defined (CONFIG_SOFT_I2C)
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#if 0 /* push-pull */
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#define SDA 0x00800000
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#define SCL 0x00000008
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#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
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#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
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#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
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#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
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#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
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#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
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#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;}
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#define I2C_READ ((IN1&SDA)?1:0)
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#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;}
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#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;}
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#define I2C_DELAY {udelay(5);}
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#define I2C_ACTIVE {DIR1|=SDA;}
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#define I2C_TRISTATE {DIR1&=~SDA;}
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#else /* open-collector */
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#define SDA 0x00800000
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#define SCL 0x00000008
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#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
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#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
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#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
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#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
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#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
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#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
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#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
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#define I2C_READ ((IN1&SDA)?1:0)
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#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;}
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#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;}
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#define I2C_DELAY {udelay(5);}
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#define I2C_ACTIVE {DIR1|=SDA;}
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#define I2C_TRISTATE {DIR1&=~SDA;}
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#endif
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#endif
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR 0x20000000
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/
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#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
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#define CFG_FLASH_BASE 0xffc00000
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#if 0 /* test-only */
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#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
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#endif
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
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#define CFG_MONITOR_LEN 0x20000
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#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
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#define CFG_BOOTPARAMS_LEN 64*1024
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
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#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16
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/*-----------------------------------------------------------------------
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* Memory bank definitions
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*/
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/* CS0 - AMD Flash, address 0xffc00000 */
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#define CFG_CSAR0 0xffc0
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#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
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/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
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#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
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/* CS1 - FPGA, address 0xe0000000 */
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#define CFG_CSAR1 0xe000
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#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
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#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
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/*-----------------------------------------------------------------------
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* Port configuration
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*/
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#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
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#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
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#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
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#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
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#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
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#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
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#define CFG_GPIO1_LED 0x00400000 /* user led */
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/*-----------------------------------------------------------------------
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* FPGA stuff
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*/
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#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
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#define CFG_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/
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/* FPGA program pin configuration */
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#define CFG_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */
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#define CFG_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */
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#define CFG_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */
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#define CFG_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */
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#define CFG_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */
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#endif /* _TASREG_H */
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