upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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96 lines
2.9 KiB
96 lines
2.9 KiB
16 years ago
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/*
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* (C) Copyright 2008 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* omap3 L2 cache code
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/cache.h>
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void l2_cache_enable(void)
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{
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unsigned long i;
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volatile unsigned int j;
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/* ES2 onwards we can disable/enable L2 ourselves */
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if (get_cpu_rev() >= CPU_3XX_ES20) {
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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} else {
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/* Save r0, r12 and restore them after usage */
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__asm__ __volatile__("mov %0, r12":"=r"(j));
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__asm__ __volatile__("mov %0, r0":"=r"(i));
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/*
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* GP Device ROM code API usage here
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* r12 = AUXCR Write function and r0 value
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*/
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__asm__ __volatile__("mov r12, #0x3");
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__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
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__asm__ __volatile__("orr r0, r0, #0x2");
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/* SMI instruction to call ROM Code API */
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__asm__ __volatile__(".word 0xE1600070");
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__asm__ __volatile__("mov r0, %0":"=r"(i));
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__asm__ __volatile__("mov r12, %0":"=r"(j));
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}
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}
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void l2_cache_disable(void)
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{
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unsigned long i;
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volatile unsigned int j;
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/* ES2 onwards we can disable/enable L2 ourselves */
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if (get_cpu_rev() >= CPU_3XX_ES20) {
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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} else {
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/* Save r0, r12 and restore them after usage */
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__asm__ __volatile__("mov %0, r12":"=r"(j));
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__asm__ __volatile__("mov %0, r0":"=r"(i));
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/*
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* GP Device ROM code API usage here
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* r12 = AUXCR Write function and r0 value
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*/
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__asm__ __volatile__("mov r12, #0x3");
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__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
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__asm__ __volatile__("bic r0, r0, #0x2");
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/* SMI instruction to call ROM Code API */
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__asm__ __volatile__(".word 0xE1600070");
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__asm__ __volatile__("mov r0, %0":"=r"(i));
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__asm__ __volatile__("mov r12, %0":"=r"(j));
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}
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}
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