upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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144 lines
3.9 KiB
144 lines
3.9 KiB
18 years ago
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/*
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* Register definitions for SDRAM Controller
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*/
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#ifndef __ASM_AVR32_HSDRAMC1_H__
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#define __ASM_AVR32_HSDRAMC1_H__
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/* HSDRAMC1 register offsets */
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#define HSDRAMC1_MR 0x0000
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#define HSDRAMC1_TR 0x0004
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#define HSDRAMC1_CR 0x0008
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#define HSDRAMC1_HSR 0x000c
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#define HSDRAMC1_LPR 0x0010
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#define HSDRAMC1_IER 0x0014
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#define HSDRAMC1_IDR 0x0018
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#define HSDRAMC1_IMR 0x001c
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#define HSDRAMC1_ISR 0x0020
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#define HSDRAMC1_MDR 0x0024
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#define HSDRAMC1_VERSION 0x00fc
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/* Bitfields in MR */
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#define HSDRAMC1_MODE_OFFSET 0
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#define HSDRAMC1_MODE_SIZE 3
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/* Bitfields in TR */
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#define HSDRAMC1_COUNT_OFFSET 0
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#define HSDRAMC1_COUNT_SIZE 12
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/* Bitfields in CR */
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#define HSDRAMC1_NC_OFFSET 0
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#define HSDRAMC1_NC_SIZE 2
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#define HSDRAMC1_NR_OFFSET 2
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#define HSDRAMC1_NR_SIZE 2
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#define HSDRAMC1_NB_OFFSET 4
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#define HSDRAMC1_NB_SIZE 1
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#define HSDRAMC1_CAS_OFFSET 5
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#define HSDRAMC1_CAS_SIZE 2
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#define HSDRAMC1_DBW_OFFSET 7
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#define HSDRAMC1_DBW_SIZE 1
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#define HSDRAMC1_TWR_OFFSET 8
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#define HSDRAMC1_TWR_SIZE 4
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#define HSDRAMC1_TRC_OFFSET 12
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#define HSDRAMC1_TRC_SIZE 4
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#define HSDRAMC1_TRP_OFFSET 16
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#define HSDRAMC1_TRP_SIZE 4
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#define HSDRAMC1_TRCD_OFFSET 20
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#define HSDRAMC1_TRCD_SIZE 4
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#define HSDRAMC1_TRAS_OFFSET 24
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#define HSDRAMC1_TRAS_SIZE 4
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#define HSDRAMC1_TXSR_OFFSET 28
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#define HSDRAMC1_TXSR_SIZE 4
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/* Bitfields in HSR */
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#define HSDRAMC1_DA_OFFSET 0
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#define HSDRAMC1_DA_SIZE 1
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/* Bitfields in LPR */
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#define HSDRAMC1_LPCB_OFFSET 0
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#define HSDRAMC1_LPCB_SIZE 2
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#define HSDRAMC1_PASR_OFFSET 4
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#define HSDRAMC1_PASR_SIZE 3
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#define HSDRAMC1_TCSR_OFFSET 8
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#define HSDRAMC1_TCSR_SIZE 2
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#define HSDRAMC1_DS_OFFSET 10
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#define HSDRAMC1_DS_SIZE 2
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#define HSDRAMC1_TIMEOUT_OFFSET 12
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#define HSDRAMC1_TIMEOUT_SIZE 2
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/* Bitfields in IDR */
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#define HSDRAMC1_RES_OFFSET 0
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#define HSDRAMC1_RES_SIZE 1
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/* Bitfields in MDR */
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#define HSDRAMC1_MD_OFFSET 0
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#define HSDRAMC1_MD_SIZE 2
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/* Bitfields in VERSION */
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#define HSDRAMC1_VERSION_OFFSET 0
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#define HSDRAMC1_VERSION_SIZE 12
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#define HSDRAMC1_MFN_OFFSET 16
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#define HSDRAMC1_MFN_SIZE 3
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/* Constants for MODE */
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#define HSDRAMC1_MODE_NORMAL 0
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#define HSDRAMC1_MODE_NOP 1
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#define HSDRAMC1_MODE_BANKS_PRECHARGE 2
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#define HSDRAMC1_MODE_LOAD_MODE 3
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#define HSDRAMC1_MODE_AUTO_REFRESH 4
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#define HSDRAMC1_MODE_EXT_LOAD_MODE 5
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#define HSDRAMC1_MODE_POWER_DOWN 6
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/* Constants for NC */
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#define HSDRAMC1_NC_8_COLUMN_BITS 0
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#define HSDRAMC1_NC_9_COLUMN_BITS 1
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#define HSDRAMC1_NC_10_COLUMN_BITS 2
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#define HSDRAMC1_NC_11_COLUMN_BITS 3
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/* Constants for NR */
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#define HSDRAMC1_NR_11_ROW_BITS 0
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#define HSDRAMC1_NR_12_ROW_BITS 1
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#define HSDRAMC1_NR_13_ROW_BITS 2
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/* Constants for NB */
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#define HSDRAMC1_NB_TWO_BANKS 0
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#define HSDRAMC1_NB_FOUR_BANKS 1
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/* Constants for CAS */
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#define HSDRAMC1_CAS_ONE_CYCLE 1
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#define HSDRAMC1_CAS_TWO_CYCLES 2
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/* Constants for DBW */
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#define HSDRAMC1_DBW_32_BITS 0
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#define HSDRAMC1_DBW_16_BITS 1
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/* Constants for TIMEOUT */
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#define HSDRAMC1_TIMEOUT_AFTER_END 0
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#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1
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#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2
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/* Constants for MD */
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#define HSDRAMC1_MD_SDRAM 0
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#define HSDRAMC1_MD_LOW_POWER_SDRAM 1
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/* Bit manipulation macros */
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#define HSDRAMC1_BIT(name) \
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(1 << HSDRAMC1_##name##_OFFSET)
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#define HSDRAMC1_BF(name,value) \
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(((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) \
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<< HSDRAMC1_##name##_OFFSET)
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#define HSDRAMC1_BFEXT(name,value) \
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(((value) >> HSDRAMC1_##name##_OFFSET) \
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& ((1 << HSDRAMC1_##name##_SIZE) - 1))
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#define HSDRAMC1_BFINS(name,value,old) \
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(((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) \
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<< HSDRAMC1_##name##_OFFSET)) \
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| HSDRAMC1_BF(name,value))
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/* Register access macros */
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#define hsdramc1_readl(port,reg) \
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readl((port)->regs + HSDRAMC1_##reg)
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#define hsdramc1_writel(port,reg,value) \
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writel((value), (port)->regs + HSDRAMC1_##reg)
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#endif /* __ASM_AVR32_HSDRAMC1_H__ */
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