upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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144 lines
3.5 KiB
144 lines
3.5 KiB
22 years ago
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#ifndef ARTICIAS_H
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#define ARTICIAS_H
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#include "short_types.h"
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#include <common.h>
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#define REG_GROUP 0xF0
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/* ArticiaS registers */
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#define GLOBALINFO0 0x50
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#define GLOBALINFO1 0x51
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#define GLOBALINFO2 0x52
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#define GLOBALINFO3 0x53
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#define GLOBALCTL0 0x54
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#define GLOBALCTL1 0x55
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#define NVRAMCTL 0x56
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#define PCI1ACR0 0x58
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#define PCI1ACR1 0x59
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#define PCI1ACR2 0x5a
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#define PCI1ACR3 0x5b
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#define HBUSACR0 0x5c
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#define HBUSACR1 0x5d
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#define HBUSACR2 0x5e
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#define HBUSACR3 0x5f
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#define HOSTINT0 0x68
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#define HOSTINT1 0x69
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#define HOSTINT2 0x6a
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#define HOSTINT3 0x6b
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#define HOSTRBCR 0x70
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#define XDBCR 0x74
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#define LBSBCR2 0xd2
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/* Memory controller */
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#define DIMM0_B0_SCR0 0x90
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#define DIMM0_B1_SCR0 0x94
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#define DIMM1_B2_SCR0 0x98
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#define DIMM1_B3_SCR0 0x9c
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#define DIMM2_B4_SCR0 0xa0
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#define DIMM2_B5_SCR0 0xa4
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#define DIMM3_B6_SCR0 0xa8
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#define DIMM3_B7_SCR0 0xac
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#define DIMM0_TCR0 0xb0
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#define DIMM1_TCR0 0xb2
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#define DIMM2_TCR0 0xb4
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#define DIMM3_TCR0 0xb6
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#define DRAM_REFRESH0 0xb8
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#define DRAM_GCR0 0xc0
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#define DRAM_PCR0 0xc6
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#define DRAM_ECC0 0xc4
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#define SRAM_CR 0xc8
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#define DRAM_RAS_CTL0 0xcc
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#define DRAM_RAS_CTL1 0xcd
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/* Bits for REG_GROUP */
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#define REG_GROUP_MULTI (1<<1)
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#define REG_GROUP_SPECIAL (1<<3)
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#define REG_GROUP_DIAG (0x1<<4)
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#define REG_GROUP_POWER (0x2<<4)
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#define GLOBALINFO0_BO (1<<7)
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#define GLOBALINFO2_B1ARBITER (1<<6)
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#define HBUSACR0_CPUAPC (1<<0)
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#define HBUSACR0_NUMREQ_2 (0<<1)
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#define HBUSACR0_NUMREQ_3 (1<<1)
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#define HBUSACR0_NUMREQ_4 (2<<1)
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#define HBUSACR0_NUMREQ_MASK (7<<1)
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#define HBUSACR0_RAW (1<<6)
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#define HBUSACR0_WAIT (1<<7)
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#define HBUSACR0_RESERVED (0x30)
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#define HBUSACR2_BURST (1<<0)
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#define HBUSACR2_LAT (1<<1)
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#define HBUSACR3_LMWC_SM (1<<0)
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#define HBUSACR3_LMWC_PCI1 (1<<1)
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#define HBUSACR3_LMWC_PCI0 (1<<2)
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#define HBUSACR3_PMWC_PCI1 (1<<3)
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#define HBUSACR3_PMWC_PCI0 (1<<4)
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#define HBUSACR3_FKH (1<<5)
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#define HBUSACR3_92H_EN (1<<6)
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#define HBUSACR3_60H_64H_EN (1<<7)
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#define HOSTRBCR_PREFETCH (1<<4)
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#define XDBCR_HWTOXD (1<<0)
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#define XDBCR_KBTOXD (1<<1)
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#define XDBCR_RTCTOXD (1<<2)
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#define XDBCR_SCALE_1_1 (0x0<<3)
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#define XDBCR_SCALE_2_2 (0x1<<3)
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#define XDBCR_SCALE_3_2 (0x2<<3)
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#define XDBCR_SCALE_4_4 (0x3<<3)
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#define XDBCR_SCALE_5_8 (0x4<<3)
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#define XDBCR_SCALE_6_8 (0x5<<3)
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#define XDBCR_SCALE_8_8 (0x6<<3)
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#define XDBCR_SCALE_0_16 (0x7<<3)
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#define XDBCR_XDPROM (1<<7)
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#define LBSBCR2_1_RWAC (1<<2)
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/* PCI controller */
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#define ARTICIAS_PCI_CFGADDR 0xfec00cf8
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#define ARTICIAS_PCI_CFGDATA 0xfee00cfc
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#define ARTICIAS_PCI_BUS 0x80000000
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#define ARTICIAS_PCI_MAXSIZE 0x7cffffff
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#define ARTICIAS_PCI_PHYS 0x80000000
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#define ARTICIAS_SYS_BUS 0x00000000
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#define ARTICIAS_SYS_MAXSIZE 0x7fffffff
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#define ARTICIAS_SYS_PHYS 0x00000000
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#define ARTICIAS_PCIIO_BUS 0x00800000
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#define ARTICIAS_PCIIO_MAXSIZE 0x003fffff
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#define ARTICIAS_PCIIO_PHYS 0xfe800000
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#define ARTICIAS_ISAIO_BUS 0x00002000
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#define ARTICIAS_ISAIO_MAXSIZE 0x0000d000
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#define ARTICIAS_ISAIO_PHYS 0xfe002000
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/* Prototypes */
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long articiaS_ram_init(void);
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void articiaS_pci_init(void);
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#endif
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