upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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58 lines
2.0 KiB
58 lines
2.0 KiB
22 years ago
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#ifndef GLUE_H
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#define GLUE_H
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typedef unsigned int pci_dev_t;
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int mypci_find_device(int vendor, int product, int index);
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int mypci_bus(int device);
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int mypci_devfn(int device);
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unsigned long get_bar_size(pci_dev_t dev, int offset);
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u8 mypci_read_cfg_byte(int bus, int devfn, int offset);
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u16 mypci_read_cfg_word(int bus, int devfn, int offset);
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u32 mypci_read_cfg_long(int bus, int devfn, int offset);
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void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value);
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void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value);
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void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value);
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void _printf(const char *fmt, ...);
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char *_getenv(char *name);
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void *malloc(size_t size);
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void memset(void *addr, int value, size_t size);
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void memcpy(void *to, void *from, size_t numbytes);
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int strcmp(char *, char *);
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void enable_compatibility_hole(void);
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void disable_compatibility_hole(void);
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void map_rom(pci_dev_t dev, unsigned long address);
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void unmap_rom(pci_dev_t dev);
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int attempt_map_rom(pci_dev_t dev, void *copy_address);
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#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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#define PCI_BUS(d) (((d) >> 16) & 0xff)
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#define PCI_DEV(d) (((d) >> 11) & 0x1f)
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#define PCI_FUNC(d) (((d) >> 8) & 0x7)
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#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
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#define PCI_ANY_ID (~0)
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define OFF(addr) ((addr) & 0xFFFF)
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#define SEG(addr) (((addr)>>4) &0xF000)
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#endif
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