upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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77 lines
1.8 KiB
77 lines
1.8 KiB
17 years ago
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/*
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* Copyright (C) 2007,2008
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ide.h>
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#include <asm/processor.h>
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#include <asm/pci.h>
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int checkboard(void)
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{
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puts("BOARD: Renesas Solutions R2D Plus\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_memstart = CFG_SDRAM_BASE;
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gd->bd->bi_memsize = CFG_SDRAM_SIZE;
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printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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#define FPGA_BASE 0xA4000000
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#define FPGA_CFCTL (FPGA_BASE + 0x04)
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#define FPGA_CFPOW (FPGA_BASE + 0x06)
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#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
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void ide_set_reset (int idereset)
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{
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/* if reset = 1 IDE reset will be asserted */
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if (idereset){
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(*(vu_short *)FPGA_CFCTL) = 0x432;
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(*(vu_short *)FPGA_CFPOW) |= 0x02;
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(*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
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}
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}
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#if defined(CONFIG_PCI)
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static struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_sh7751_init( &hose );
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}
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#endif /* CONFIG_PCI */
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