upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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84 lines
2.3 KiB
84 lines
2.3 KiB
18 years ago
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/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/sections.h>
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#include <asm/sysreg.h>
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#include <asm/arch/memory-map.h>
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#include <asm/arch/platform.h>
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#include "hsmc3.h"
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DECLARE_GLOBAL_DATA_PTR;
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int cpu_init(void)
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{
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const struct device *hebi;
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extern void _evba(void);
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char *p;
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gd->cpu_hz = CFG_OSC0_HZ;
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/* fff03400: 00010001 04030402 00050005 10011103 */
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hebi = get_device(DEVICE_HEBI);
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hsmc3_writel(hebi, MODE0, 0x00031103);
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hsmc3_writel(hebi, CYCLE0, 0x000c000d);
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hsmc3_writel(hebi, PULSE0, 0x0b0a0906);
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hsmc3_writel(hebi, SETUP0, 0x00010002);
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pm_init();
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sysreg_write(EVBA, (unsigned long)&_evba);
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asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
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gd->console_uart = get_device(CFG_CONSOLE_UART_DEV);
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/* Lock everything that mess with the flash in the icache */
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for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
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p += CFG_ICACHE_LINESZ)
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asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
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return 0;
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}
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void prepare_to_boot(void)
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{
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/* Flush both caches and the write buffer */
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asm volatile("cache %0[4], 010\n\t"
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"cache %0[0], 000\n\t"
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"sync 0" : : "r"(0) : "memory");
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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/* This will reset the CPU core, caches, MMU and all internal busses */
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__builtin_mtdr(8, 1 << 13); /* set DC:DBE */
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__builtin_mtdr(8, 1 << 30); /* set DC:RES */
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/* Flush the pipeline before we declare it a failure */
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asm volatile("sub pc, pc, -4");
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return -1;
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}
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