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/*
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* mcf5271.h -- Definitions for Motorola Coldfire 5271
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*
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* (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
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* Based on mcf5272sim.h of uCLinux distribution:
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* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _MCF5271_H_
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#define _MCF5271_H_
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#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
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#define mbar_readShort(x) *((volatile unsigned short *) (CFG_MBAR + x))
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#define mbar_readByte(x) *((volatile unsigned char *) (CFG_MBAR + x))
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#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
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#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
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#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
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#define MCF_FMPLL_SYNCR 0x120000
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#define MCF_FMPLL_SYNSR 0x120004
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#define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
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#define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19)
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#define MCF_FMPLL_SYNSR_LOCK 0x8
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#define MCF_WTM_WCR 0x140000
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#define MCF_WTM_WCNTR 0x140004
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#define MCF_WTM_WSR 0x140006
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#define MCF_WTM_WCR_EN 0x0001
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#define MCF_RCM_RCR 0x110000
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#define MCF_RCM_RCR_FRCRSTOUT 0x40
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#define MCF_RCM_RCR_SOFTRST 0x80
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#define MCF_GPIO_PAR_AD 0x100040
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#define MCF_GPIO_PAR_CS 0x100045
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#define MCF_GPIO_PAR_SDRAM 0x100046
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#define MCF_GPIO_PAR_FECI2C 0x100047
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#define MCF_GPIO_PAR_UART 0x100048
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#define MCF_GPIO_AD_ADDR23 0x80
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#define MCF_GPIO_AD_ADDR22 0x40
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#define MCF_GPIO_AD_ADDR21 0x20
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#define MCF_GPIO_AD_DATAL 0x01
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#define MCF_GPIO_AD_MASK 0xe1
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#define MCF_GPIO_PAR_CS_PAR_CS2 0x04
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#define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */
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#define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */
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#define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */
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#define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */
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#define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */
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#define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */
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#define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */
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#define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */
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#define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */
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#define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */
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#define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */
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#define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
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#define MCF_GPIO_PAR_UART_U0RTS 0x0001
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#define MCF_GPIO_PAR_UART_U0CTS 0x0002
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#define MCF_GPIO_PAR_UART_U0TXD 0x0004
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#define MCF_GPIO_PAR_UART_U0RXD 0x0008
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#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
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#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
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#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
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#define MCF_SDRAMC_DCR 0x000040
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#define MCF_SDRAMC_DACR0 0x000048
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#define MCF_SDRAMC_DMR0 0x00004C
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#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
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#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
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#define MCF_SDRAMC_DCR_IS 0x0800
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#define MCF_SDRAMC_DCR_COC 0x1000
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#define MCF_SDRAMC_DCR_NAM 0x2000
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#define MCF_SDRAMC_DACRn_IP 0x00000008
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#define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4)
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#define MCF_SDRAMC_DACRn_MRS 0x00000040
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#define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8)
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#define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12)
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#define MCF_SDRAMC_DACRn_RE 0x00008000
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#define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18)
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#define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000
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#define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000
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#define MCF_SDRAMC_DMRn_V 0x00000001
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#define MCFSIM_ICR1 0x000C41
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#endif /* _MCF5271_H_ */
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