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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 2,
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.rank_density = 2147483648u,
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.capacity = 4294967296u,
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.primary_sdram_width = 64,
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.ec_sdram_width = 8,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 2, /* ECC */
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 1071,
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.caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
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.taa_ps = 13125,
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.twr_ps = 15000,
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.trcd_ps = 13125,
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.trrd_ps = 6000,
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.trp_ps = 13125,
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.tras_ps = 34000,
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.trc_ps = 48125,
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.trfc_ps = 260000,
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.twtr_ps = 7500,
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.trtp_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tfaw_ps = 35000,
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};
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2
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*/
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{2, 833, 4, 4, 6, 0x06060607, 0x08080807},
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{2, 833, 0, 4, 6, 0x06060607, 0x08080807},
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{2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
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{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
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{2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
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{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
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{1, 833, 4, 4, 6, 0x06060607, 0x08080807},
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{1, 833, 0, 4, 6, 0x06060607, 0x08080807},
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{1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
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{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
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{1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
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{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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