upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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164 lines
6.7 KiB
164 lines
6.7 KiB
24 years ago
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/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
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/*
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* acceptable chips types are:
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*
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* 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
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*/
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/* register addresses, valid only following an CHIP_CMD_RD_ID command */
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#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
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#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
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#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
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#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
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/* Commands */
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#define CHIP_CMD_RST 0xFF /* reset flash */
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#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
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#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
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#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
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#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
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#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
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#define CHIP_CMD_PROG 0x40 /* program word command */
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#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
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#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
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#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
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#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
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#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
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#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
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#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
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/* status register bits */
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#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
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#define CHIP_STAT_VPPS 0x08 /* VPP Status */
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#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
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#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
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#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
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#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
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#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
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CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
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/* ID and Lock Configuration */
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#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
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#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
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#define CHIP_RD_ID_DEV CFG_FLASH_ID
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/* dimensions */
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#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
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#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
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#define CHIP_NBLOCKS CFG_FLASH_NBLOCKS
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#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
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#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
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/********************** DEFINES for Hymod Flash ******************************/
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/*
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* The hymod board has 2 x 28F320J5 chips running in
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* 16 bit mode, for a 32 bit wide bank.
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*/
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typedef unsigned long bank_word_t; /* 8/16/32/64bit unsigned int */
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typedef volatile bank_word_t *bank_addr_t;
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typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
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#define BANK_CHIP_WIDTH 2 /* each bank is 2 chips wide */
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#define BANK_CHIP_WSHIFT 1 /* (log2 of BANK_CHIP_WIDTH) */
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#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
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#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
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#define BANK_NBLOCKS CHIP_NBLOCKS
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#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
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#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
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#define MAX_BANKS 1 /* only one bank possible */
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/* align bank addresses and sizes to bank word boundaries */
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#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
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& ~(BANK_WIDTH - 1)))
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#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
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(bank_size_t)(s) + (BANK_WIDTH - 1)))
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/* align bank addresses and sizes to bank block boundaries */
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#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
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& ~(BANK_BLKSZ - 1)))
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#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
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(bank_size_t)(s) + (BANK_BLKSZ - 1)))
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/* align bank addresses and sizes to bank boundaries */
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#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
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& ~(BANK_SIZE - 1)))
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#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
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(bank_size_t)(s) + (BANK_SIZE - 1)))
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/* add an offset to a bank address */
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#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
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(bank_size_t)(o))
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/* get base address of bank b, given flash base address a */
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#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
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(bank_size_t)(b) * BANK_SIZE)
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/* adjust a bank address to start of next word, block or bank */
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#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
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BANK_WIDTH)
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#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
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BANK_BLKSZ)
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#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
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BANK_SIZE)
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/* get bank address of chip register r given a bank base address a */
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#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
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((bank_size_t)(r) << BANK_WSHIFT))
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/* make a bank address for each chip register address */
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#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
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#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
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#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
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#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
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/*
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* replicate a chip cmd/stat/rd value into each byte position within a word
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* so that multiple chips are accessed in a single word i/o operation
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*
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* this must be as wide as the bank_word_t type, and take into account the
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* chip width and bank layout
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*/
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#define BANK_FILL_WORD(o) ((bank_word_t)( \
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((unsigned long)(o) << 16) | \
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((unsigned long)(o) << 0) \
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))
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/* make a bank word value for each chip cmd/stat/rd value */
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/* Commands */
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#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
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#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
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#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
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#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
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#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
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#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
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#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
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#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
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#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
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#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
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#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
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/* status register bits */
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#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
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#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
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#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
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#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
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#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
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#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
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#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
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#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
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/* ID and Lock Configuration */
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#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
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#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
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#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
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