upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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138 lines
4.0 KiB
138 lines
4.0 KiB
18 years ago
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/*
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* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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* Changed by HuTao Apr18, 2003
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*
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* Copyright was missing when I got the code so took from MIPS arch ...MaTed---
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* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
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* Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
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*
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* Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
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* Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
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* Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
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*
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* Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
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* Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
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* Copyright (c) 2004 LG Soft India.
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* Copyright (c) 2004 HHTech.
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*
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* Adapted for BlackFin BF561 by Bas Vermeulen <bas@buyways.nl>
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* Copyright (c) 2005 BuyWays B.V. (www.buyways.nl)
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*/
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#ifndef _BF561_IRQ_H_
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#define _BF561_IRQ_H_
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/*
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* Interrupt source definitions:
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* Event Source Core Event Name IRQ No
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* Emulation Events EMU 0
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* Reset RST 1
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* NMI NMI 2
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* Exception EVX 3
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* Reserved -- 4
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* Hardware Error IVHW 5
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* Core Timer IVTMR 6
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*
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* PLL Wakeup Interrupt IVG7 7
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* DMA1 Error (generic) IVG7 8
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* DMA2 Error (generic) IVG7 9
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* IMDMA Error (generic) IVG7 10
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* PPI1 Error Interrupt IVG7 11
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* PPI2 Error Interrupt IVG7 12
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* SPORT0 Error Interrupt IVG7 13
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* SPORT1 Error Interrupt IVG7 14
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* SPI Error Interrupt IVG7 15
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* UART Error Interrupt IVG7 16
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* Reserved Interrupt IVG7 17
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*
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* DMA1 0 Interrupt(PPI1) IVG8 18
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* DMA1 1 Interrupt(PPI2) IVG8 19
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* DMA1 2 Interrupt IVG8 20
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* DMA1 3 Interrupt IVG8 21
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* DMA1 4 Interrupt IVG8 22
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* DMA1 5 Interrupt IVG8 23
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* DMA1 6 Interrupt IVG8 24
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* DMA1 7 Interrupt IVG8 25
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* DMA1 8 Interrupt IVG8 26
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* DMA1 9 Interrupt IVG8 27
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* DMA1 10 Interrupt IVG8 28
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* DMA1 11 Interrupt IVG8 29
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*
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* DMA2 0 (SPORT0 RX) IVG9 30
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* DMA2 1 (SPORT0 TX) IVG9 31
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* DMA2 2 (SPORT1 RX) IVG9 32
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* DMA2 3 (SPORT2 TX) IVG9 33
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* DMA2 4 (SPI) IVG9 34
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* DMA2 5 (UART RX) IVG9 35
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* DMA2 6 (UART TX) IVG9 36
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* DMA2 7 Interrupt IVG9 37
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* DMA2 8 Interrupt IVG9 38
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* DMA2 9 Interrupt IVG9 39
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* DMA2 10 Interrupt IVG9 40
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* DMA2 11 Interrupt IVG9 41
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*
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* TIMER 0 Interrupt IVG10 42
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* TIMER 1 Interrupt IVG10 43
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* TIMER 2 Interrupt IVG10 44
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* TIMER 3 Interrupt IVG10 45
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* TIMER 4 Interrupt IVG10 46
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* TIMER 5 Interrupt IVG10 47
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* TIMER 6 Interrupt IVG10 48
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* TIMER 7 Interrupt IVG10 49
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* TIMER 8 Interrupt IVG10 50
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* TIMER 9 Interrupt IVG10 51
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* TIMER 10 Interrupt IVG10 52
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* TIMER 11 Interrupt IVG10 53
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*
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* Programmable Flags0 A (8) IVG11 54
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* Programmable Flags0 B (8) IVG11 55
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* Programmable Flags1 A (8) IVG11 56
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* Programmable Flags1 B (8) IVG11 57
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* Programmable Flags2 A (8) IVG11 58
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* Programmable Flags2 B (8) IVG11 59
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*
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* MDMA1 0 write/read INT IVG8 60
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* MDMA1 1 write/read INT IVG8 61
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*
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* MDMA2 0 write/read INT IVG9 62
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* MDMA2 1 write/read INT IVG9 63
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*
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* IMDMA 0 write/read INT IVG12 64
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* IMDMA 1 write/read INT IVG12 65
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*
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* Watch Dog Timer IVG13 66
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*
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* Reserved interrupt IVG7 67
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* Reserved interrupt IVG7 68
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* Supplemental interrupt 0 IVG7 69
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* supplemental interrupt 1 IVG7 70
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*
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* Software Interrupt 1 IVG14 71
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* Software Interrupt 2 IVG15 72
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*/
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/*
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* The ABSTRACT IRQ definitions
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* the first seven of the following are fixed,
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* the rest you change if you need to.
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*/
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/* IVG 0-6 */
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#define IRQ_EMU 0 /* Emulation */
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#define IRQ_RST 1 /* Reset */
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#define IRQ_NMI 2 /* Non Maskable Interrupt */
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#define IRQ_EVX 3 /* Exception */
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#define IRQ_UNUSED 4 /* Reserved interrupt */
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#define IRQ_HWERR 5 /* Hardware Error */
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#define IRQ_CORETMR 6 /* Core timer */
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#define IRQ_UART_RX_BIT 0x10000000
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#define IRQ_UART_TX_BIT 0x20000000
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#define IRQ_UART_ERROR_BIT 0x200
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#endif /* _BF561_IRQ_H_ */
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