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upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/board/google/chromebook_samus/Kconfig

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x86: Add support for the samus chromebook This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years ago
if TARGET_CHROMEBOOK_SAMUS
config SYS_BOARD
default "chromebook_samus"
config SYS_VENDOR
default "google"
config SYS_SOC
default "broadwell"
config SYS_CONFIG_NAME
default "chromebook_samus"
config SYS_TEXT_BASE
default 0xffe00000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
select INTEL_BROADWELL
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
x86: kconfig: Let board select SPI flash Only a specific type of SPI flash exists on a board, having board Kconfig to select the SPI flash seems to make more sense. Other flash types are not necessary except coreboot, which implies all available flash drivers there. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
7 years ago
select SPI_FLASH_WINBOND
x86: Add support for the samus chromebook This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years ago
config PCIE_ECAM_BASE
default 0xf0000000
config EARLY_POST_CROS_EC
bool "Enable early post to Chrome OS EC"
default y
config SYS_CAR_ADDR
hex
default 0xff7c0000
config SYS_CAR_SIZE
hex
default 0x40000
endif