upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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113 lines
3.6 KiB
113 lines
3.6 KiB
11 years ago
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/*
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* pinmux setup for siemens dxr2 board
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*
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* (C) Copyright 2013 Siemens Schweiz AG
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* u-boot:/board/ti/am335x/mux.c
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux uart3_pin_mux[] = {
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{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
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{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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static struct module_pin_mux gpios_pin_mux[] = {
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/* DFU button GPIO0_27*/
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{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
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{OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
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{OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
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{-1},
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};
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static struct module_pin_mux ethernet_pin_mux[] = {
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{OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
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{OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
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{OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
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{OFFSET(mii1_txen), (MODE(1))},
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{OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
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{OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
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{OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
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{OFFSET(mii1_txd1), (MODE(1))},
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{OFFSET(mii1_txd0), (MODE(1))},
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{OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)},
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{OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)},
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{OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
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{OFFSET(mii1_rxd2), (MODE(1))},
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{OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
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{OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
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{OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
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{OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
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{OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
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{-1},
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};
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_uart3_pin_mux(void)
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{
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configure_module_pin_mux(uart3_pin_mux);
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}
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void enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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void enable_board_pin_mux(void)
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{
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enable_uart3_pin_mux();
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configure_module_pin_mux(nand_pin_mux);
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configure_module_pin_mux(ethernet_pin_mux);
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configure_module_pin_mux(gpios_pin_mux);
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}
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