upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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75 lines
1.7 KiB
75 lines
1.7 KiB
11 years ago
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/*
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* Copyright (C) 2013 Samsung Electronics
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* Piotr Wilczek <p.wilczek@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MAX77693_MUIC_H_
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#define __MAX77693_MUIC_H_
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#include <power/power_chrg.h>
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/*
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* MUIC REGISTER
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*/
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#define MAX77693_MUIC_PREFIX "max77693-muic:"
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/* MAX77693_MUIC_STATUS1 */
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#define MAX77693_MUIC_ADC_MASK 0x1F
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/* MAX77693_MUIC_STATUS2 */
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#define MAX77693_MUIC_CHG_NO 0x00
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#define MAX77693_MUIC_CHG_USB 0x01
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#define MAX77693_MUIC_CHG_USB_D 0x02
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#define MAX77693_MUIC_CHG_TA 0x03
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#define MAX77693_MUIC_CHG_TA_500 0x04
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#define MAX77693_MUIC_CHG_TA_1A 0x05
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#define MAX77693_MUIC_CHG_MASK 0x07
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/* MAX77693_MUIC_CONTROL1 */
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#define MAX77693_MUIC_CTRL1_DN1DP2 ((0x1 << 3) | 0x1)
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#define MAX77693_MUIC_CTRL1_UT1UR2 ((0x3 << 3) | 0x3)
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#define MAX77693_MUIC_CTRL1_ADN1ADP2 ((0x4 << 3) | 0x4)
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#define MAX77693_MUIC_CTRL1_AUT1AUR2 ((0x5 << 3) | 0x5)
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#define MAX77693_MUIC_CTRL1_MASK 0xC0
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#define MUIC_PATH_USB 0
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#define MUIC_PATH_UART 1
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#define MUIC_PATH_CP 0
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#define MUIC_PATH_AP 1
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enum muic_path {
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MUIC_PATH_USB_CP,
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MUIC_PATH_USB_AP,
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MUIC_PATH_UART_CP,
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MUIC_PATH_UART_AP,
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};
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/* MAX 777693 MUIC registers */
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enum {
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MAX77693_MUIC_ID = 0x00,
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MAX77693_MUIC_INT1 = 0x01,
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MAX77693_MUIC_INT2 = 0x02,
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MAX77693_MUIC_INT3 = 0x03,
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MAX77693_MUIC_STATUS1 = 0x04,
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MAX77693_MUIC_STATUS2 = 0x05,
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MAX77693_MUIC_STATUS3 = 0x06,
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MAX77693_MUIC_INTMASK1 = 0x07,
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MAX77693_MUIC_INTMASK2 = 0x08,
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MAX77693_MUIC_INTMASK3 = 0x09,
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MAX77693_MUIC_CDETCTRL = 0x0A,
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MAX77693_MUIC_CONTROL1 = 0x0C,
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MAX77693_MUIC_CONTROL2 = 0x0D,
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MAX77693_MUIC_CONTROL3 = 0x0E,
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MUIC_NUM_OF_REGS = 0x0F,
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};
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#define MAX77693_MUIC_I2C_ADDR (0x4A >> 1)
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int power_muic_init(unsigned int bus);
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#endif /* __MAX77693_MUIC_H_ */
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