upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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59 lines
1.5 KiB
59 lines
1.5 KiB
15 years ago
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/*
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* PLL setup for Cirrus edb93xx boards
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*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include "pll_cfg.h"
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#include "early_udelay.h"
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void pll_cfg(void)
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{
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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/* setup PLL1 */
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writel(CLKSET1_VAL, &syscon->clkset1);
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/*
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* flush the pipeline
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* writing to CLKSET1 causes the EP93xx to enter standby for between
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* 8 ms to 16 ms, until PLL1 stabilizes
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*/
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asm("nop");
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asm("nop");
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asm("nop");
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asm("nop");
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asm("nop");
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/* setup PLL2 */
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writel(CLKSET2_VAL, &syscon->clkset2);
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/*
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* the user's guide recommends to wait at least 1 ms for PLL2 to
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* stabilize
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*/
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early_udelay(1000);
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}
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