upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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73 lines
2.6 KiB
73 lines
2.6 KiB
15 years ago
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/*
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* PLL register values for Cirrus edb93xx boards
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*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/ep93xx.h>
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#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
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defined(CONFIG_EDB9302A)
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/*
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* fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
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* pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
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* pll1_x2: 331776000.000000, pll1_out: 331776000.000000
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*/
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#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
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8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
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3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
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SYSCON_CLKSET1_NBYP1 | \
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1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
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#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
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defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
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defined(CONFIG_EDB9315A)
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/*
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* fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
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* pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
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* pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
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*/
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#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
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30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
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2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
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SYSCON_CLKSET1_NBYP1 | \
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1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
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#else
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#error "Undefined board"
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#endif
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/*
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* usb_div: 4, nbyp2: 1, pll2_en: 1
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* pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
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* pll2_x2: 384000000.000000, pll2_out: 192000000.000000
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*/
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#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
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SYSCON_CLKSET2_PLL2_EN | \
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SYSCON_CLKSET2_NBYP2 | \
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3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
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