upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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172 lines
5.4 KiB
172 lines
5.4 KiB
18 years ago
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/*
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* uart.h -- ColdFire internal UART support defines.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/****************************************************************************/
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#ifndef uart_h
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#define uart_h
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/****************************************************************************/
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/* UART module registers */
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/* Register read/write struct */
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typedef struct uart {
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u8 umr; /* 0x00 Mode Register */
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u8 resv0[0x3];
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union {
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u8 usr; /* 0x04 Status Register */
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u8 ucsr; /* 0x04 Clock Select Register */
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};
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u8 resv1[0x3];
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u8 ucr; /* 0x08 Command Register */
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u8 resv2[0x3];
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union {
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u8 utb; /* 0x0c Transmit Buffer */
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u8 urb; /* 0x0c Receive Buffer */
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};
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u8 resv3[0x3];
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union {
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u8 uipcr; /* 0x10 Input Port Change Register */
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u8 uacr; /* 0x10 Auxiliary Control reg */
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};
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u8 resv4[0x3];
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union {
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u8 uimr; /* 0x14 Interrupt Mask reg */
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u8 uisr; /* 0x14 Interrupt Status reg */
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};
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u8 resv5[0x3];
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u8 ubg1; /* 0x18 Counter Timer Upper Register */
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u8 resv6[0x3];
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u8 ubg2; /* 0x1c Counter Timer Lower Register */
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u8 resv7[0x17];
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u8 uip; /* 0x34 Input Port Register */
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u8 resv8[0x3];
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u8 uop1; /* 0x38 Output Port Set Register */
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u8 resv9[0x3];
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u8 uop0; /* 0x3c Output Port Reset Register */
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} uart_t;
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/*********************************************************************
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* Universal Asynchronous Receiver Transmitter (UART)
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*********************************************************************/
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/* Bit definitions and macros for UMR */
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#define UART_UMR_BC(x) (((x)&0x03))
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#define UART_UMR_PT (0x04)
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#define UART_UMR_PM(x) (((x)&0x03)<<3)
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#define UART_UMR_ERR (0x20)
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#define UART_UMR_RXIRQ (0x40)
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#define UART_UMR_RXRTS (0x80)
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#define UART_UMR_SB(x) (((x)&0x0F))
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#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
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#define UART_UMR_TXRTS (0x20) /* Transmit RTS */
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#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
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#define UART_UMR_PM_MULTI_ADDR (0x1C)
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#define UART_UMR_PM_MULTI_DATA (0x18)
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#define UART_UMR_PM_NONE (0x10)
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#define UART_UMR_PM_FORCE_HI (0x0C)
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#define UART_UMR_PM_FORCE_LO (0x08)
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#define UART_UMR_PM_ODD (0x04)
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#define UART_UMR_PM_EVEN (0x00)
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#define UART_UMR_BC_5 (0x00)
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#define UART_UMR_BC_6 (0x01)
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#define UART_UMR_BC_7 (0x02)
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#define UART_UMR_BC_8 (0x03)
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#define UART_UMR_CM_NORMAL (0x00)
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#define UART_UMR_CM_ECH (0x40)
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#define UART_UMR_CM_LOCAL_LOOP (0x80)
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#define UART_UMR_CM_REMOTE_LOOP (0xC0)
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#define UART_UMR_SB_STOP_BITS_1 (0x07)
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#define UART_UMR_SB_STOP_BITS_15 (0x08)
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#define UART_UMR_SB_STOP_BITS_2 (0x0F)
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/* Bit definitions and macros for USR */
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#define UART_USR_RXRDY (0x01)
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#define UART_USR_FFULL (0x02)
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#define UART_USR_TXRDY (0x04)
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#define UART_USR_TXEMP (0x08)
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#define UART_USR_OE (0x10)
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#define UART_USR_PE (0x20)
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#define UART_USR_FE (0x40)
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#define UART_USR_RB (0x80)
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/* Bit definitions and macros for UCSR */
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#define UART_UCSR_TCS(x) (((x)&0x0F))
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#define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
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#define UART_UCSR_RCS_SYS_CLK (0xD0)
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#define UART_UCSR_RCS_CTM16 (0xE0)
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#define UART_UCSR_RCS_CTM (0xF0)
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#define UART_UCSR_TCS_SYS_CLK (0x0D)
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#define UART_UCSR_TCS_CTM16 (0x0E)
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#define UART_UCSR_TCS_CTM (0x0F)
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/* Bit definitions and macros for UCR */
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#define UART_UCR_RXC(x) (((x)&0x03))
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#define UART_UCR_TXC(x) (((x)&0x03)<<2)
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#define UART_UCR_MISC(x) (((x)&0x07)<<4)
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#define UART_UCR_NONE (0x00)
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#define UART_UCR_STOP_BREAK (0x70)
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#define UART_UCR_START_BREAK (0x60)
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#define UART_UCR_BKCHGINT (0x50)
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#define UART_UCR_RESET_ERROR (0x40)
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#define UART_UCR_RESET_TX (0x30)
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#define UART_UCR_RESET_RX (0x20)
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#define UART_UCR_RESET_MR (0x10)
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#define UART_UCR_TX_DISABLED (0x08)
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#define UART_UCR_TX_ENABLED (0x04)
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#define UART_UCR_RX_DISABLED (0x02)
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#define UART_UCR_RX_ENABLED (0x01)
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/* Bit definitions and macros for UIPCR */
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#define UART_UIPCR_CTS (0x01)
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#define UART_UIPCR_COS (0x10)
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/* Bit definitions and macros for UACR */
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#define UART_UACR_IEC (0x01)
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/* Bit definitions and macros for UIMR */
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#define UART_UIMR_TXRDY (0x01)
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#define UART_UIMR_RXRDY_FU (0x02)
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#define UART_UIMR_DB (0x04)
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#define UART_UIMR_COS (0x80)
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/* Bit definitions and macros for UISR */
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#define UART_UISR_TXRDY (0x01)
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#define UART_UISR_RXRDY_FU (0x02)
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#define UART_UISR_DB (0x04)
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#define UART_UISR_RXFTO (0x08)
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#define UART_UISR_TXFIFO (0x10)
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#define UART_UISR_RXFIFO (0x20)
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#define UART_UISR_COS (0x80)
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/* Bit definitions and macros for UIP */
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#define UART_UIP_CTS (0x01)
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/* Bit definitions and macros for UOP1 */
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#define UART_UOP1_RTS (0x01)
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/* Bit definitions and macros for UOP0 */
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#define UART_UOP0_RTS (0x01)
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/****************************************************************************/
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#endif /* mcfuart_h */
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