upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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584 lines
18 KiB
584 lines
18 KiB
23 years ago
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/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*
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* Most of these definitions are derived from
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* linux/drivers/scsi/sym53c8xx_defs.h
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*
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*/
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#ifndef _SYM53C8XX_DEFS_H
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#define _SYM53C8XX_DEFS_H
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#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
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#define SCNTL1 0x01 /* no reset */
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#define ISCON 0x10 /* connected to scsi */
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#define CRST 0x08 /* force reset */
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#define IARB 0x02 /* immediate arbitration */
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#define SCNTL2 0x02 /* no disconnect expected */
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#define SDU 0x80 /* cmd: disconnect will raise error */
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#define CHM 0x40 /* sta: chained mode */
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#define WSS 0x08 /* sta: wide scsi send [W]*/
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#define WSR 0x01 /* sta: wide scsi received [W]*/
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#define SCNTL3 0x03 /* cnf system clock dependent */
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#define EWS 0x08 /* cmd: enable wide scsi [W]*/
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#define ULTRA 0x80 /* cmd: ULTRA enable */
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/* bits 0-2, 7 rsvd for C1010 */
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#define SCID 0x04 /* cnf host adapter scsi address */
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#define RRE 0x40 /* r/w:e enable response to resel. */
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#define SRE 0x20 /* r/w:e enable response to select */
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#define SXFER 0x05 /* ### Sync speed and count */
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/* bits 6-7 rsvd for C1010 */
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#define SDID 0x06 /* ### Destination-ID */
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#define GPREG 0x07 /* ??? IO-Pins */
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#define SFBR 0x08 /* ### First byte in phase */
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#define SOCL 0x09
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#define CREQ 0x80 /* r/w: SCSI-REQ */
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#define CACK 0x40 /* r/w: SCSI-ACK */
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#define CBSY 0x20 /* r/w: SCSI-BSY */
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#define CSEL 0x10 /* r/w: SCSI-SEL */
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#define CATN 0x08 /* r/w: SCSI-ATN */
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#define CMSG 0x04 /* r/w: SCSI-MSG */
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#define CC_D 0x02 /* r/w: SCSI-C_D */
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#define CI_O 0x01 /* r/w: SCSI-I_O */
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#define SSID 0x0a
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#define SBCL 0x0b
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#define DSTAT 0x0c
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#define DFE 0x80 /* sta: dma fifo empty */
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#define MDPE 0x40 /* int: master data parity error */
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#define BF 0x20 /* int: script: bus fault */
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#define ABRT 0x10 /* int: script: command aborted */
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#define SSI 0x08 /* int: script: single step */
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#define SIR 0x04 /* int: script: interrupt instruct. */
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#define IID 0x01 /* int: script: illegal instruct. */
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#define SSTAT0 0x0d
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#define ILF 0x80 /* sta: data in SIDL register lsb */
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#define ORF 0x40 /* sta: data in SODR register lsb */
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#define OLF 0x20 /* sta: data in SODL register lsb */
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#define AIP 0x10 /* sta: arbitration in progress */
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#define LOA 0x08 /* sta: arbitration lost */
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#define WOA 0x04 /* sta: arbitration won */
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#define IRST 0x02 /* sta: scsi reset signal */
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#define SDP 0x01 /* sta: scsi parity signal */
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#define SSTAT1 0x0e
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#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
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#define SSTAT2 0x0f
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#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
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#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
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#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
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#define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
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#define LDSC 0x02 /* sta: disconnect & reconnect */
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#define DSA 0x10 /* --> Base page */
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#define DSA1 0x11
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#define DSA2 0x12
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#define DSA3 0x13
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#define ISTAT 0x14 /* --> Main Command and status */
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#define CABRT 0x80 /* cmd: abort current operation */
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#define SRST 0x40 /* mod: reset chip */
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#define SIGP 0x20 /* r/w: message from host to ncr */
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#define SEM 0x10 /* r/w: message between host + ncr */
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#define CON 0x08 /* sta: connected to scsi */
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#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
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#define SIP 0x02 /* sta: scsi-interrupt */
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#define DIP 0x01 /* sta: host/script interrupt */
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#define CTEST0 0x18
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#define CTEST1 0x19
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#define CTEST2 0x1a
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#define CSIGP 0x40
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/* bits 0-2,7 rsvd for C1010 */
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#define CTEST3 0x1b
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#define FLF 0x08 /* cmd: flush dma fifo */
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#define CLF 0x04 /* cmd: clear dma fifo */
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#define FM 0x02 /* mod: fetch pin mode */
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#define WRIE 0x01 /* mod: write and invalidate enable */
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/* bits 4-7 rsvd for C1010 */
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#define DFIFO 0x20
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#define CTEST4 0x21
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#define BDIS 0x80 /* mod: burst disable */
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#define MPEE 0x08 /* mod: master parity error enable */
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#define CTEST5 0x22
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#define DFS 0x20 /* mod: dma fifo size */
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/* bits 0-1, 3-7 rsvd for C1010 */
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#define CTEST6 0x23
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#define DBC 0x24 /* ### Byte count and command */
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#define DNAD 0x28 /* ### Next command register */
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#define DSP 0x2c /* --> Script Pointer */
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#define DSPS 0x30 /* --> Script pointer save/opcode#2 */
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#define SCRATCHA 0x34 /* Temporary register a */
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#define SCRATCHA1 0x35
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#define SCRATCHA2 0x36
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#define SCRATCHA3 0x37
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#define DMODE 0x38
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#define BL_2 0x80 /* mod: burst length shift value +2 */
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#define BL_1 0x40 /* mod: burst length shift value +1 */
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#define ERL 0x08 /* mod: enable read line */
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#define ERMP 0x04 /* mod: enable read multiple */
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#define BOF 0x02 /* mod: burst op code fetch */
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#define MAN 0x01 /* mod: manual start */
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#define DIEN 0x39
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#define SBR 0x3a
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#define DCNTL 0x3b /* --> Script execution control */
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#define CLSE 0x80 /* mod: cache line size enable */
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#define PFF 0x40 /* cmd: pre-fetch flush */
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#define PFEN 0x20 /* mod: pre-fetch enable */
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#define SSM 0x10 /* mod: single step mode */
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#define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
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#define STD 0x04 /* cmd: start dma mode */
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#define IRQD 0x02 /* mod: irq disable */
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#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
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/* bits 0-1 rsvd for C1010 */
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#define ADDER 0x3c
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#define SIEN 0x40 /* -->: interrupt enable */
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#define SIST 0x42 /* <--: interrupt status */
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#define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
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#define STO 0x0400/* sta: timeout (select) */
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#define GEN 0x0200/* sta: timeout (general) */
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#define HTH 0x0100/* sta: timeout (handshake) */
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#define MA 0x80 /* sta: phase mismatch */
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#define CMP 0x40 /* sta: arbitration complete */
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#define SEL 0x20 /* sta: selected by another device */
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#define RSL 0x10 /* sta: reselected by another device*/
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#define SGE 0x08 /* sta: gross error (over/underflow)*/
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#define UDC 0x04 /* sta: unexpected disconnect */
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#define RST 0x02 /* sta: scsi bus reset detected */
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#define PAR 0x01 /* sta: scsi parity error */
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#define SLPAR 0x44
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#define SWIDE 0x45
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#define MACNTL 0x46
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#define GPCNTL 0x47
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#define STIME0 0x48 /* cmd: timeout for select&handshake*/
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#define STIME1 0x49 /* cmd: timeout user defined */
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#define RESPID 0x4a /* sta: Reselect-IDs */
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#define STEST0 0x4c
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#define STEST1 0x4d
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#define SCLK 0x80 /* Use the PCI clock as SCSI clock */
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#define DBLEN 0x08 /* clock doubler running */
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#define DBLSEL 0x04 /* clock doubler selected */
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#define STEST2 0x4e
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#define ROF 0x40 /* reset scsi offset (after gross error!) */
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#define EXT 0x02 /* extended filtering */
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#define STEST3 0x4f
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#define TE 0x80 /* c: tolerAnt enable */
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#define HSC 0x20 /* c: Halt SCSI Clock */
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#define CSF 0x02 /* c: clear scsi fifo */
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#define SIDL 0x50 /* Lowlevel: latched from scsi data */
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#define STEST4 0x52
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#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
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#define SMODE_HVD 0x40 /* High Voltage Differential */
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#define SMODE_SE 0x80 /* Single Ended */
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#define SMODE_LVD 0xc0 /* Low Voltage Differential */
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#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
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/* bits 0-5 rsvd for C1010 */
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#define SODL 0x54 /* Lowlevel: data out to scsi data */
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#define SBDL 0x58 /* Lowlevel: data from scsi data */
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/*-----------------------------------------------------------
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||
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**
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** Utility macros for the script.
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||
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**
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||
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**-----------------------------------------------------------
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||
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*/
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||
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#define REG(r) (r)
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||
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/*-----------------------------------------------------------
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**
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** SCSI phases
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**
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** DT phases illegal for ncr driver.
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||
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**
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||
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**-----------------------------------------------------------
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||
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*/
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||
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#define SCR_DATA_OUT 0x00000000
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#define SCR_DATA_IN 0x01000000
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#define SCR_COMMAND 0x02000000
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||
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#define SCR_STATUS 0x03000000
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||
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#define SCR_DT_DATA_OUT 0x04000000
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||
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#define SCR_DT_DATA_IN 0x05000000
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||
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#define SCR_MSG_OUT 0x06000000
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||
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#define SCR_MSG_IN 0x07000000
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||
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||
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#define SCR_ILG_OUT 0x04000000
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||
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#define SCR_ILG_IN 0x05000000
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||
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||
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/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** Data transfer via SCSI.
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
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|
** MOVE_ABS (LEN)
|
||
|
|
** <<start address>>
|
||
|
|
**
|
||
|
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** MOVE_IND (LEN)
|
||
|
|
** <<dnad_offset>>
|
||
|
|
**
|
||
|
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** MOVE_TBL
|
||
|
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** <<dnad_offset>>
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
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|
|
||
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|
#define OPC_MOVE 0x08000000
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||
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|
||
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|
#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
|
||
|
|
#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
|
||
|
|
#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
|
||
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|
||
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#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
|
||
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#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
|
||
|
|
#define SCR_CHMOV_TBL (0x10000000)
|
||
|
|
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** Selection
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
|
||
|
|
** <<alternate_address>>
|
||
|
|
**
|
||
|
|
** SEL_TBL | << dnad_offset>> [ | REL_JMP]
|
||
|
|
** <<alternate_address>>
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
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||
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|
||
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|
#define SCR_SEL_ABS 0x40000000
|
||
|
|
#define SCR_SEL_ABS_ATN 0x41000000
|
||
|
|
#define SCR_SEL_TBL 0x42000000
|
||
|
|
#define SCR_SEL_TBL_ATN 0x43000000
|
||
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|
||
|
|
|
||
|
|
#define SCR_JMP_REL 0x04000000
|
||
|
|
#define SCR_ID(id) (((unsigned long)(id)) << 16)
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** Waiting for Disconnect or Reselect
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** WAIT_DISC
|
||
|
|
** dummy: <<alternate_address>>
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||
|
|
**
|
||
|
|
** WAIT_RESEL
|
||
|
|
** <<alternate_address>>
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
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|
||
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|
#define SCR_WAIT_DISC 0x48000000
|
||
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|
#define SCR_WAIT_RESEL 0x50000000
|
||
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|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** Bit Set / Reset
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** SET (flags {|.. })
|
||
|
|
**
|
||
|
|
** CLR (flags {|.. })
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
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|
|
||
|
|
#define SCR_SET(f) (0x58000000 | (f))
|
||
|
|
#define SCR_CLR(f) (0x60000000 | (f))
|
||
|
|
|
||
|
|
#define SCR_CARRY 0x00000400
|
||
|
|
#define SCR_TRG 0x00000200
|
||
|
|
#define SCR_ACK 0x00000040
|
||
|
|
#define SCR_ATN 0x00000008
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** Memory to memory move
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** COPY (bytecount)
|
||
|
|
** << source_address >>
|
||
|
|
** << destination_address >>
|
||
|
|
**
|
||
|
|
** SCR_COPY sets the NO FLUSH option by default.
|
||
|
|
** SCR_COPY_F does not set this option.
|
||
|
|
**
|
||
|
|
** For chips which do not support this option,
|
||
|
|
** ncr_copy_and_bind() will remove this bit.
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define SCR_NO_FLUSH 0x01000000
|
||
|
|
|
||
|
|
#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
|
||
|
|
#define SCR_COPY_F(n) (0xc0000000 | (n))
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** Register move and binary operations
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** SFBR_REG (reg, op, data) reg = SFBR op data
|
||
|
|
** << 0 >>
|
||
|
|
**
|
||
|
|
** REG_SFBR (reg, op, data) SFBR = reg op data
|
||
|
|
** << 0 >>
|
||
|
|
**
|
||
|
|
** REG_REG (reg, op, data) reg = reg op data
|
||
|
|
** << 0 >>
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
** On 810A, 860, 825A, 875, 895 and 896 chips the content
|
||
|
|
** of SFBR register can be used as data (SCR_SFBR_DATA).
|
||
|
|
** The 896 has additionnal IO registers starting at
|
||
|
|
** offset 0x80. Bit 7 of register offset is stored in
|
||
|
|
** bit 7 of the SCRIPTS instruction first DWORD.
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
|
||
|
|
|
||
|
|
#define SCR_SFBR_REG(reg,op,data) \
|
||
|
|
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
||
|
|
|
||
|
|
#define SCR_REG_SFBR(reg,op,data) \
|
||
|
|
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
||
|
|
|
||
|
|
#define SCR_REG_REG(reg,op,data) \
|
||
|
|
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
|
||
|
|
|
||
|
|
|
||
|
|
#define SCR_LOAD 0x00000000
|
||
|
|
#define SCR_SHL 0x01000000
|
||
|
|
#define SCR_OR 0x02000000
|
||
|
|
#define SCR_XOR 0x03000000
|
||
|
|
#define SCR_AND 0x04000000
|
||
|
|
#define SCR_SHR 0x05000000
|
||
|
|
#define SCR_ADD 0x06000000
|
||
|
|
#define SCR_ADDC 0x07000000
|
||
|
|
|
||
|
|
#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** FROM_REG (reg) SFBR = reg
|
||
|
|
** << 0 >>
|
||
|
|
**
|
||
|
|
** TO_REG (reg) reg = SFBR
|
||
|
|
** << 0 >>
|
||
|
|
**
|
||
|
|
** LOAD_REG (reg, data) reg = <data>
|
||
|
|
** << 0 >>
|
||
|
|
**
|
||
|
|
** LOAD_SFBR(data) SFBR = <data>
|
||
|
|
** << 0 >>
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define SCR_FROM_REG(reg) \
|
||
|
|
SCR_REG_SFBR(reg,SCR_OR,0)
|
||
|
|
|
||
|
|
#define SCR_TO_REG(reg) \
|
||
|
|
SCR_SFBR_REG(reg,SCR_OR,0)
|
||
|
|
|
||
|
|
#define SCR_LOAD_REG(reg,data) \
|
||
|
|
SCR_REG_REG(reg,SCR_LOAD,data)
|
||
|
|
|
||
|
|
#define SCR_LOAD_SFBR(data) \
|
||
|
|
(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** LOAD from memory to register.
|
||
|
|
** STORE from register to memory.
|
||
|
|
**
|
||
|
|
** Only supported by 810A, 860, 825A, 875, 895 and 896.
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** LOAD_ABS (LEN)
|
||
|
|
** <<start address>>
|
||
|
|
**
|
||
|
|
** LOAD_REL (LEN) (DSA relative)
|
||
|
|
** <<dsa_offset>>
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
|
||
|
|
#define SCR_NO_FLUSH2 0x02000000
|
||
|
|
#define SCR_DSA_REL2 0x10000000
|
||
|
|
|
||
|
|
#define SCR_LOAD_R(reg, how, n) \
|
||
|
|
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
|
||
|
|
|
||
|
|
#define SCR_STORE_R(reg, how, n) \
|
||
|
|
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
|
||
|
|
|
||
|
|
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
|
||
|
|
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
|
||
|
|
#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
|
||
|
|
#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
|
||
|
|
|
||
|
|
#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
|
||
|
|
#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
|
||
|
|
#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
|
||
|
|
#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
|
||
|
|
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** Waiting for Disconnect or Reselect
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
**
|
||
|
|
** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
|
||
|
|
** <<address>>
|
||
|
|
**
|
||
|
|
** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
|
||
|
|
** <<distance>>
|
||
|
|
**
|
||
|
|
** CALL [ | IFTRUE/IFFALSE ( ... ) ]
|
||
|
|
** <<address>>
|
||
|
|
**
|
||
|
|
** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
|
||
|
|
** <<distance>>
|
||
|
|
**
|
||
|
|
** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
|
||
|
|
** <<dummy>>
|
||
|
|
**
|
||
|
|
** INT [ | IFTRUE/IFFALSE ( ... ) ]
|
||
|
|
** <<ident>>
|
||
|
|
**
|
||
|
|
** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
|
||
|
|
** <<ident>>
|
||
|
|
**
|
||
|
|
** Conditions:
|
||
|
|
** WHEN (phase)
|
||
|
|
** IF (phase)
|
||
|
|
** CARRYSET
|
||
|
|
** DATA (data, mask)
|
||
|
|
**
|
||
|
|
**-----------------------------------------------------------
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define SCR_NO_OP 0x80000000
|
||
|
|
#define SCR_JUMP 0x80080000
|
||
|
|
#define SCR_JUMP64 0x80480000
|
||
|
|
#define SCR_JUMPR 0x80880000
|
||
|
|
#define SCR_CALL 0x88080000
|
||
|
|
#define SCR_CALLR 0x88880000
|
||
|
|
#define SCR_RETURN 0x90080000
|
||
|
|
#define SCR_INT 0x98080000
|
||
|
|
#define SCR_INT_FLY 0x98180000
|
||
|
|
|
||
|
|
#define IFFALSE(arg) (0x00080000 | (arg))
|
||
|
|
#define IFTRUE(arg) (0x00000000 | (arg))
|
||
|
|
|
||
|
|
#define WHEN(phase) (0x00030000 | (phase))
|
||
|
|
#define IF(phase) (0x00020000 | (phase))
|
||
|
|
|
||
|
|
#define DATA(D) (0x00040000 | ((D) & 0xff))
|
||
|
|
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
|
||
|
|
|
||
|
|
#define CARRYSET (0x00200000)
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#define SIR_COMPLETE 0x10000000
|
||
|
|
/* script errors */
|
||
|
|
#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
|
||
|
|
#define SIR_CMD_OUT_ILL_PH 0x00000002
|
||
|
|
#define SIR_STATUS_ILL_PH 0x00000003
|
||
|
|
#define SIR_MSG_RECEIVED 0x00000004
|
||
|
|
#define SIR_DATA_IN_ERR 0x00000005
|
||
|
|
#define SIR_DATA_OUT_ERR 0x00000006
|
||
|
|
#define SIR_SCRIPT_ERROR 0x00000007
|
||
|
|
#define SIR_MSG_OUT_NO_CMD 0x00000008
|
||
|
|
#define SIR_MSG_OVER7 0x00000009
|
||
|
|
/* Fly interrupt */
|
||
|
|
#define INT_ON_FY 0x00000080
|
||
|
|
|
||
|
|
/* Hardware errors are defined in scsi.h */
|
||
|
|
|
||
|
|
#define SCSI_IDENTIFY 0xC0
|
||
|
|
|
||
|
|
#ifndef TRUE
|
||
|
|
#define TRUE 1
|
||
|
|
#endif
|
||
|
|
#ifndef FALSE
|
||
|
|
#define FALSE 0
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|